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| author | stroese <stroese> | 2003-03-25 14:41:35 +0000 |
|---|---|---|
| committer | stroese <stroese> | 2003-03-25 14:41:35 +0000 |
| commit | d69b100e7038ccf7a760dad973ec4a7a35c81e9c (patch) | |
| tree | 5ef1e6707d1cd47e9306dd9347bbb0a0d82c471d /include/configs/PCI405.h | |
| parent | 5d5d44e71787014b409eca6714229d3357c6c000 (diff) | |
| download | u-boot-imx-d69b100e7038ccf7a760dad973ec4a7a35c81e9c.zip u-boot-imx-d69b100e7038ccf7a760dad973ec4a7a35c81e9c.tar.gz u-boot-imx-d69b100e7038ccf7a760dad973ec4a7a35c81e9c.tar.bz2 | |
esd PCI405 updated.
Diffstat (limited to 'include/configs/PCI405.h')
| -rw-r--r-- | include/configs/PCI405.h | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 3f9b8d4..39fdf55 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -40,9 +40,13 @@ #define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ +#if 1 /* test-only */ #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ +#else +#define CONFIG_SYS_CLK_FREQ 16000000 /* external frequency to pll */ +#endif -#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #if 0 @@ -78,6 +82,7 @@ CFG_CMD_ELF | \ CFG_CMD_DATE | \ CFG_CMD_I2C | \ + CFG_CMD_BSP | \ CFG_CMD_EEPROM ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -87,6 +92,8 @@ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ + /* * Miscellaneous configurable options */ @@ -128,7 +135,7 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /*----------------------------------------------------------------------- * PCI stuff @@ -149,7 +156,7 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ #define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #if 0 /* test-only */ @@ -158,8 +165,8 @@ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ #else #define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */ -#define CFG_PCI_PTM2MS 0xef600001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ #endif /*----------------------------------------------------------------------- @@ -269,6 +276,7 @@ /* Memory Bank 2 (CAN0, 1) initialization */ #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +//#define CFG_EBC_PB2AP 0x038056C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 3 (FPGA internal) initialization */ @@ -319,19 +327,13 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ -#if 1 /* test-only */ #define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#else -#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#endif #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - /* * Internal Definitions * |