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| author | stroese <stroese> | 2004-12-16 18:05:42 +0000 |
|---|---|---|
| committer | stroese <stroese> | 2004-12-16 18:05:42 +0000 |
| commit | a20b27a36b7b1f593e18b4efd506e5f01a392dc6 (patch) | |
| tree | f9dc45c287966bb96c38a8267d07b217727efb3c /include/configs/PCI405.h | |
| parent | 44acc8d334a8b9ddb81fc238b094574991f19afa (diff) | |
| download | u-boot-imx-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.zip u-boot-imx-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.tar.gz u-boot-imx-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.tar.bz2 | |
esd config files updated
Diffstat (limited to 'include/configs/PCI405.h')
| -rw-r--r-- | include/configs/PCI405.h | 49 |
1 files changed, 30 insertions, 19 deletions
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 49fdfdd..2671125 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001 + * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -42,27 +42,21 @@ #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ + #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 0 -#define CONFIG_PREBOOT \ - "crc32 f0207004 ffc 0;" \ - "if cmp 0 f0207000 1;" \ - "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ - "else;echo Old CRC is bad;fi" -#endif +#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */ #undef CONFIG_BOOTARGS -#if 1 -#define CONFIG_BOOTCOMMAND \ - "bootm fffc0000" -#else -#define CONFIG_BOOTCOMMAND \ - "mw.l 0 ffffffff; mw.l 4 ffffffff;" \ - "while cmp 0 4 1; do echo Waiting for Host...;done;" \ - "bootm 400000" -#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mem_linux=14336k\0" \ + "optargs=panic=0\0" \ + "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ + "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ + "" +#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci" + +#define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -321,16 +315,33 @@ #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ #define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ #define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ +/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */ +#define CFG_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ +#if 0 /* test-only */ #define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#endif /* * Internal Definitions |