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| author | Liu Gang <Gang.Liu@freescale.com> | 2014-05-15 14:30:34 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-05-16 16:29:16 -0500 |
| commit | e4911815cf98237b65a817a3c791f143794f2837 (patch) | |
| tree | ad3f8b2fd41c5c5443b3897ad6e3b18e4e8bdc7f /include/configs/P2041RDB.h | |
| parent | 3246584d194d3d8f0354fd2fbeef5a8d1f00769e (diff) | |
| download | u-boot-imx-e4911815cf98237b65a817a3c791f143794f2837.zip u-boot-imx-e4911815cf98237b65a817a3c791f143794f2837.tar.gz u-boot-imx-e4911815cf98237b65a817a3c791f143794f2837.tar.bz2 | |
powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE boot
The new 768KB u-boot image size requires changes for
SRIO/PCIE boot. These addresses need to be updated to
appropriate locations.
The updated addresses are used to configure the SRIO/PCIE
inbound windows for the boot, and they must be aligned
with the window size based on the SRIO/PCIE modules requirement.
So for the 768KB u-boot image, the inbound window cannot be set
with 0xfff40000 base address and 0xc0000 size, it should be
extended to 1MB size and the base address can be aligned with
the size.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs/P2041RDB.h')
| -rw-r--r-- | include/configs/P2041RDB.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e662322..16f7525 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -381,15 +381,15 @@ unsigned long get_board_sys_clk(unsigned long dummy); * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ |