diff options
| author | Shaohui Xie <Shaohui.Xie@freescale.com> | 2012-02-28 23:28:07 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-04-24 23:58:31 -0500 |
| commit | c9b2feafaaf0a7998347589f9a29f7169873af6e (patch) | |
| tree | 32833e5b3a236d5e52f521aa6cf7ba7f7d23369a /include/configs/P2041RDB.h | |
| parent | 1ba62f10172ead798a8176435cfffff2f79f21c5 (diff) | |
| download | u-boot-imx-c9b2feafaaf0a7998347589f9a29f7169873af6e.zip u-boot-imx-c9b2feafaaf0a7998347589f9a29f7169873af6e.tar.gz u-boot-imx-c9b2feafaaf0a7998347589f9a29f7169873af6e.tar.bz2 | |
powerpc/p2041rdb: add NAND and NAND boot support
New P2041RDB board will add a NAND chip, so add support for NAND and
NAND boot.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/P2041RDB.h')
| -rw-r--r-- | include/configs/P2041RDB.h | 54 |
1 files changed, 51 insertions, 3 deletions
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index da98f8f..501726c 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -186,10 +186,11 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM \ +#define CONFIG_SYS_FLASH_BR_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ - | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) +#define CONFIG_SYS_FLASH_OR_PRELIM \ + ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) #define CONFIG_FSL_CPLD #define CPLD_BASE 0xffdf0000 /* CPLD registers */ @@ -221,6 +222,53 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_RAMBOOT #endif +#define CONFIG_NAND_FSL_ELBC +/* Nand Flash */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#ifdef CONFIG_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ +#endif /* CONFIG_NAND_FSL_ELBC */ + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |