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authorShaohui Xie <Shaohui.Xie@freescale.com>2011-09-13 17:55:11 +0800
committerKumar Gala <galak@kernel.crashing.org>2011-10-03 08:30:02 -0500
commit44d50f0b54ef14534440bc5d789ec65240dfc0f8 (patch)
tree3abda67a24ea3aca853e69ef631d6837c6346329 /include/configs/P2041RDB.h
parentba50fee6ae7e626bb2eda9d28403d7d3950f407a (diff)
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powerpc/p2041rdb: set sysclk according to status of physical switch SW1
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software need to read the SW1 status to decide what the sysclk needs. SW1[8~6] : frequency 0 0 1 : 83.3MHz 0 1 0 : 100MHz others: 66.667MHz Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/P2041RDB.h')
-rw-r--r--include/configs/P2041RDB.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 37e98bb..c7f0761 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -102,7 +102,10 @@
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#define CONFIG_SYS_CLK_FREQ 66666666
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
/*
* These can be toggled for performance analysis, otherwise use default.