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| author | Wolfgang Denk <wd@denx.de> | 2009-07-07 20:54:12 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-07-07 20:54:12 +0200 |
| commit | 73e1140b4929c92f7715bbc64ee8553815bb43aa (patch) | |
| tree | 337677f8f62440561b93dca1053f6105c2c880c2 /include/configs/P2020DS.h | |
| parent | 98ab14e858bf60306d0aa3f0df5a7a5f88264aff (diff) | |
| parent | afb0b1315c048ce2b1f35f0183b8b118ad0c14e1 (diff) | |
| download | u-boot-imx-73e1140b4929c92f7715bbc64ee8553815bb43aa.zip u-boot-imx-73e1140b4929c92f7715bbc64ee8553815bb43aa.tar.gz u-boot-imx-73e1140b4929c92f7715bbc64ee8553815bb43aa.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include/configs/P2020DS.h')
| -rw-r--r-- | include/configs/P2020DS.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a39ff26..fddcce5 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -46,6 +46,7 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -437,7 +438,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 @@ -456,7 +457,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -475,7 +476,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |