summaryrefslogtreecommitdiff
path: root/include/configs/P2020DS.h
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2010-05-21 03:02:16 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-16 10:55:08 -0500
commitebf9d5261efc7a60eac54b675b67e3c7ab614f60 (patch)
treebbf3e11442008d74cef1194eab3a7d773d2b6304 /include/configs/P2020DS.h
parentb4a60e521c66b1e634cacdebcfae3a1e1c9deb52 (diff)
downloadu-boot-imx-ebf9d5261efc7a60eac54b675b67e3c7ab614f60.zip
u-boot-imx-ebf9d5261efc7a60eac54b675b67e3c7ab614f60.tar.gz
u-boot-imx-ebf9d5261efc7a60eac54b675b67e3c7ab614f60.tar.bz2
Move ICS CLK chip frequency calculation code into a common board library
We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'include/configs/P2020DS.h')
-rw-r--r--include/configs/P2020DS.h16
1 files changed, 5 insertions, 11 deletions
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 66be725..9955501 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include "../board/freescale/common/ics307_clk.h"
+
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT
#endif
@@ -54,17 +56,9 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#ifndef __ASSEMBLY__
-extern unsigned long calculate_board_sys_clk(unsigned long dummy);
-extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
-/* extern unsigned long get_board_sys_clk(unsigned long dummy); */
-/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
-#endif
-#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
- from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.