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authorPoonam Aggrwal <poonam.aggrwal@freescale.com>2009-08-21 07:29:58 +0530
committerKumar Gala <galak@kernel.crashing.org>2009-08-28 17:12:46 -0500
commit33f3f34255bd7cf0be502275c59f0ff22dc50080 (patch)
tree607daa0460bd787ee986bf94ad50982a97ebac0a /include/configs/P1_P2_RDB.h
parent0d3d68b25a8e7790f58530ddccbd61f9fc0245ef (diff)
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85xx: Added PCIe support for P1 P2 RDB
Call fsl_pci_init_port() to initialize all the PCIe ports on the board. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/P1_P2_RDB.h')
-rw-r--r--include/configs/P1_P2_RDB.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 9591641..6d44d6c 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -35,6 +35,12 @@
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE