Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 74 insertions, 74 deletions

diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index 1f4c329..9182223 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -53,7 +53,7 @@
 #define CONFIG_BOOTCOMMAND	"bootm 400e0000"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 #undef	CONFIG_WATCHDOG			/* watchdog disabled, for now	    */
 #define CONFIG_AUTOSCRIPT
 
@@ -81,25 +81,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -109,64 +109,64 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define xEMBED
 #ifdef	EMBED
 #define CONFIG_ENV_SIZE		0x200	/* FIXME How big when embedded?? */
-#define CONFIG_ENV_ADDR		CFG_MONITOR_BASE
+#define CONFIG_ENV_ADDR		CONFIG_SYS_MONITOR_BASE
 #else
 #define CONFIG_ENV_ADDR		0x40020000	/* absolute address for now   */
 #define CONFIG_ENV_SIZE		0x20000 /* 8K ouch, this may later be */
 #endif
 
-#define CFG_FLASH_SN_BASE	0x4001fff0	/* programmer automagically puts    */
-#define CFG_FLASH_SN_SECTOR	0x40000000	/* a serial number here		    */
-#define CFG_FLASH_SN_BYTES	8
+#define CONFIG_SYS_FLASH_SN_BASE	0x4001fff0	/* programmer automagically puts    */
+#define CONFIG_SYS_FLASH_SN_SECTOR	0x40000000	/* a serial number here		    */
+#define CONFIG_SYS_FLASH_SN_BYTES	8
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value    */
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value    */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -176,10 +176,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -187,27 +187,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				12-16
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		12-18
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		12-23
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		5-7
@@ -218,8 +218,8 @@
 #define MPC8XX_SPEED	66666666L
 #define MPC8XX_XIN	32768	/* 32.768 kHz crystal */
 #define MPC8XX_FACT		(MPC8XX_SPEED/MPC8XX_XIN)
-#define CFG_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
-#define CFG_PLPRCR		(CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
+#define CONFIG_SYS_PLPRCR		(CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		5-3
@@ -228,7 +228,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -238,7 +238,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /*
  * Init Memory Controller:
@@ -252,16 +252,16 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
 				 OR_SCY_8_CLK )
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR1/2 and OR1/2 (SDRAM)
@@ -271,12 +271,12 @@
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
-#define CFG_OR_TIMING_SDRAM	(OR_G5LS | OR_CSNT_SAM)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS | OR_CSNT_SAM)
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CFG_OR2_PRELIM	CFG_OR1_PRELIM
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR1_PRELIM
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* IO and memory mapped stuff */
 #define NX823_IO_OR_AM		0xFFFF0000	/* mask for IO addresses */
@@ -292,24 +292,24 @@
  */
 #define GPOUT_BASE	(NX823_IO_BASE + GPOUT_OFFSET)
 #define GPOUT_TIMING	(OR_CSNT_SAM | OR_TRLX | OR_BI)
-#define CFG_OR3_PRELIM	(NX823_IO_OR_AM | GPOUT_TIMING)
-#define CFG_BR3_PRELIM	(GPOUT_BASE | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	(NX823_IO_OR_AM | GPOUT_TIMING)
+#define CONFIG_SYS_BR3_PRELIM	(GPOUT_BASE | BR_V)
 
 /*
  * BR4 and OR4 (QUART)
  */
 #define QUART_BASE	(NX823_IO_BASE + QUART_OFFSET)
 #define QUART_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
-#define CFG_OR4_PRELIM	(NX823_IO_OR_AM | QUART_TIMING | OR_BI)
-#define CFG_BR4_PRELIM	(QUART_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR4_PRELIM	(NX823_IO_OR_AM | QUART_TIMING | OR_BI)
+#define CONFIG_SYS_BR4_PRELIM	(QUART_BASE | BR_PS_8 | BR_V)
 
 /*
  * BR5 and OR5 (Video DAC)
  */
 #define VIDAC_BASE	(NX823_IO_BASE + VIDAC_OFFSET)
 #define VIDAC_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CFG_OR5_PRELIM	(NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
-#define CFG_BR5_PRELIM	(VIDAC_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR5_PRELIM	(NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
+#define CONFIG_SYS_BR5_PRELIM	(VIDAC_BASE | BR_PS_8 | BR_V)
 
 /*
  * BR6 and OR6 (CPLD)
@@ -317,42 +317,42 @@
  */
 #define CPLD_BASE	(NX823_IO_BASE + CPLD_OFFSET)
 #define CPLD_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CFG_OR6_PRELIM	(NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
-#define CFG_BR6_PRELIM	(CPLD_BASE | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR6_PRELIM	(NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
+#define CONFIG_SYS_BR6_PRELIM	(CPLD_BASE | BR_PS_8 | BR_V )
 
 /*
  * BR7 and OR7 (SED1386)
  * FIXME timing not verified for SED controller
  */
 #define SED1386_BASE	0xF7000000
-#define CFG_OR7_PRELIM	(0xFF000000 | OR_BI | OR_SETA)
-#define CFG_BR7_PRELIM	(SED1386_BASE | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR7_PRELIM	(0xFF000000 | OR_BI | OR_SETA)
+#define CONFIG_SYS_BR7_PRELIM	(SED1386_BASE | BR_PS_16 | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz   */
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz   */
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16 /* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32 /* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16 /* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32 /* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16 /* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8	/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16 /* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)