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| author | Kim Phillips <kim.phillips@freescale.com> | 2009-09-25 18:19:44 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-09-26 21:19:38 -0500 |
| commit | c7190f028fa950d4d36b6d0b4bb3fc72602ec54c (patch) | |
| tree | ea0ece278a5c2ac1bae9a1bdbe66ba796368f55f /include/configs/MVBLM7.h | |
| parent | 00ec0ff549b8cb6fb6d40e275aeb5a460642a3bd (diff) | |
| download | u-boot-imx-c7190f028fa950d4d36b6d0b4bb3fc72602ec54c.zip u-boot-imx-c7190f028fa950d4d36b6d0b4bb3fc72602ec54c.tar.gz u-boot-imx-c7190f028fa950d4d36b6d0b4bb3fc72602ec54c.tar.bz2 | |
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields
some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.
Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.
also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.
also start to use i/o accessors.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/configs/MVBLM7.h')
| -rw-r--r-- | include/configs/MVBLM7.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9835567..f8b016f 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -137,7 +137,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB sdram refresh timer, about 6us */ |