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author | wdenk <wdenk> | 2004-06-06 21:35:06 +0000 |
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committer | wdenk <wdenk> | 2004-06-06 21:35:06 +0000 |
commit | 1114257c9df3fa3db39ff55dd03d1f7cbc5c0603 (patch) | |
tree | 7d62ed142cf3c00aea35e518ed28dc9f5c6887fd /include/configs/MPC885ADS.h | |
parent | d7a04603ae9c85d496b3991f29dbb8ea339ace49 (diff) | |
download | u-boot-imx-1114257c9df3fa3db39ff55dd03d1f7cbc5c0603.zip u-boot-imx-1114257c9df3fa3db39ff55dd03d1f7cbc5c0603.tar.gz u-boot-imx-1114257c9df3fa3db39ff55dd03d1f7cbc5c0603.tar.bz2 |
Patch by Yuli Barcohen, 19 Apr 2004:
- Rename DUET_ADS to MPC885ADS
- Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
- Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
- Clean up FADS family port to use the new defines
Diffstat (limited to 'include/configs/MPC885ADS.h')
-rw-r--r-- | include/configs/MPC885ADS.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h new file mode 100644 index 0000000..7f0b06a --- /dev/null +++ b/include/configs/MPC885ADS.h @@ -0,0 +1,45 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola DUET ADS board. Values common to all FADS family boards + * are in board/fads/fads.h + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Board type */ +#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ + +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ + +#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) + +#define CONFIG_SDRAM_50MHZ 1 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +#include "fads.h" + +#undef CFG_SCCR +#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) + +#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) + +#endif /* __CONFIG_H */ |