Merge with /home/stefan/git/u-boot/u-boot-ppc4xx

1 files changed, 98 insertions, 57 deletions

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 12af24f..03e815d 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -46,8 +46,10 @@
 
 #define CFG_RESET_ADDRESS    0xfff00100
 
-/*#undef CONFIG_PCI*/
-#define CONFIG_PCI
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCI2		1	/* PCIE controler 2 (slot) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -76,6 +78,9 @@
 #define L2_ENABLE	(L2CR_L2E)
 
 #ifndef CONFIG_SYS_CLK_FREQ
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 #endif
 
@@ -93,6 +98,9 @@
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR		(CFG_CCSRBAR+0x9000)
+
 /*
  * DDR Setup
  */
@@ -232,7 +240,7 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 #define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MALLOC_LEN	    	(1024 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
@@ -296,9 +304,9 @@
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 /* PCI view of System Memory */
 #define CFG_PCI_MEMORY_BUS      0x00000000
@@ -311,10 +319,10 @@
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe3000000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -330,12 +338,43 @@
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_PCI_OHCI		1
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_USB_KEYBOARD	1
+#define CFG_DEVICE_DEREGISTER
+#define CFG_USB_EVENT_POLL	1
+#define CFG_USB_OHCI_SLOT_NAME 	"ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
     #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
 #endif
 
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CFG_PCI2_IO_PHYS
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CFG_PCI1_IO_PHYS*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS
+#endif
+
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
 #define CONFIG_DOS_PARTITION
@@ -349,6 +388,8 @@
 #define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
 #endif
 
+#define CONFIG_MPC86XX_PCI2
+
 #endif	/* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
@@ -376,6 +417,10 @@
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 
 #define CONFIG_ETHPRIME		"eTSEC1"
 
@@ -396,20 +441,20 @@
  * 0xa000_0000  512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CFG_DBAT1L      ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT1L      ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT1U	(CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CFG_IBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT1U      CFG_DBAT1U
 
 /*
  * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U      (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT2U	(CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT2U      CFG_DBAT2U
 
 /*
@@ -428,10 +473,10 @@
  * 0xe300_0000  16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CFG_DBAT4L      ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+#define CFG_DBAT4L      ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U      (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT4U	(CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT4U      CFG_DBAT4U
 
 /*
@@ -463,8 +508,8 @@
  */
 #ifndef CFG_RAMBOOT
     #define CFG_ENV_IS_IN_FLASH	1
-    #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-    #define CFG_ENV_SECT_SIZE		0x40000	/* 256K(one sector) for env */
+    #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
+    #define CFG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
     #define CFG_ENV_SIZE		0x2000
 #else
     #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
@@ -475,39 +520,34 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
 #if defined(CFG_RAMBOOT)
-  #if defined(CONFIG_PCI)
-    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
-				 | CFG_CMD_PING		\
-				 | CFG_CMD_PCI		\
-				 | CFG_CMD_I2C		\
-				 | CFG_CMD_SCSI		\
-				 | CFG_CMD_EXT2)	\
-				&			\
-				 ~(CFG_CMD_ENV))
-  #else
-    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
-				 | CFG_CMD_PING		\
-				 | CFG_CMD_I2C)		\
-				&			\
-				 ~(CFG_CMD_ENV))
-  #endif
-#else
-  #if defined(CONFIG_PCI)
-    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
-				| CFG_CMD_PCI		\
-				| CFG_CMD_PING		\
-				| CFG_CMD_I2C		\
-				| CFG_CMD_SCSI		\
-				| CFG_CMD_EXT2)
-  #else
-    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
-				| CFG_CMD_PING		\
-				| CFG_CMD_I2C)
-  #endif
+    #undef CONFIG_CMD_ENV
+#endif
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+    #define CONFIG_CMD_SCSI
+    #define CONFIG_CMD_EXT2
 #endif
 
-#include <cmd_confdefs.h>
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
@@ -518,7 +558,7 @@
 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
     #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
     #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
@@ -539,8 +579,8 @@
 /* Cache Configuration */
 #define CFG_DCACHE_SIZE		32768
 #define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#if defined(CONFIG_CMD_KGDB)
+    #define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 #endif
 
 /*
@@ -551,9 +591,9 @@
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+    #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -568,6 +608,7 @@
 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
 
+#define CONFIG_HAS_ETH0		1
 #define CONFIG_HAS_ETH1		1
 #define CONFIG_HAS_ETH2		1
 #define CONFIG_HAS_ETH3		1