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| author | Jon Loeliger <jdl@freescale.com> | 2008-11-20 14:02:56 -0600 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-12-01 10:28:49 -0600 |
| commit | f698738e46cb461e28c2d58228bb34a2fcf5a475 (patch) | |
| tree | 1a43372894a08775638028bede6c28c5d81abfd6 /include/configs/MPC8610HPCD.h | |
| parent | 2077e348c2a84901022ad95311b47b70361e6daa (diff) | |
| download | u-boot-imx-f698738e46cb461e28c2d58228bb34a2fcf5a475.zip u-boot-imx-f698738e46cb461e28c2d58228bb34a2fcf5a475.tar.gz u-boot-imx-f698738e46cb461e28c2d58228bb34a2fcf5a475.tar.bz2 | |
86xx: Fix non-64-bit compilation problems.
Introducing 64-bit (36-bit) support for the MPC8641HPCN
failed to accomodate the other two 86xx boards.
Introduce definitions for CONFIG_SYS_CCSRBAR_PHYS_{LOW,HIGH}
CONFIG_SYS_CCSR_DEFAULT_DBAT{U,L} and CONFIG_SYS_CCSR_DEFAULT_IBAT{U,L}
with nominal 32-bit values.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
Diffstat (limited to 'include/configs/MPC8610HPCD.h')
| -rw-r--r-- | include/configs/MPC8610HPCD.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index f2fe4a6..5685027 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -81,6 +81,9 @@ #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) @@ -388,6 +391,17 @@ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATU_BL_1M | BATU_VS | BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + /* * BAT4 32M Cache-inhibited, guarded * 0xe200_0000 1M PCI-Express 2 I/O |