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| author | Jon Loeliger <jdl@freescale.com> | 2008-03-18 13:51:05 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:50 -0500 |
| commit | e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e (patch) | |
| tree | f87e55ccfd5ad5a853d2fb69c0889bf4dc4991f8 /include/configs/MPC8568MDS.h | |
| parent | e31d2c1e2bc954dc32e33bb2076139f85b95f8e6 (diff) | |
| download | u-boot-imx-e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e.zip u-boot-imx-e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e.tar.gz u-boot-imx-e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e.tar.bz2 | |
FSL DDR: Convert MPC8568MDS to new DDR code.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8568MDS.h')
| -rw-r--r-- | include/configs/MPC8568MDS.h | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a82d528..8aeaa29 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -41,14 +41,6 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ - -/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ -/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* @@ -58,8 +50,6 @@ */ #define CONFIG_ASSUME_AMD_FLASH -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - #ifndef __ASSEMBLY__ extern unsigned long get_clock_freq(void); #endif /*Replace a call to get_clock_freq (after it is implemented)*/ @@ -95,24 +85,33 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) -/* - * DDR Setup - */ +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -/* - * Make sure required options are set - */ +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* Make sure required options are set */ #ifndef CONFIG_SPD_EEPROM #error ("CONFIG_SPD_EEPROM is required") #endif #undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -302,6 +301,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + /* * I2C */ |