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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-12-02 16:08:39 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
| commit | 5af0fdd81c3370c3a51421208fda568bdcbbec23 (patch) | |
| tree | 5fbd9f1b25951176fdaaa9d7eb76dd486930e6e5 /include/configs/MPC8568MDS.h | |
| parent | a6e04c344ad1eefd47a75484441b385da815b8df (diff) | |
| download | u-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.zip u-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.gz u-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.bz2 | |
85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/MPC8568MDS.h')
| -rw-r--r-- | include/configs/MPC8568MDS.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 77abe4f..fcaca1a 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -322,20 +322,23 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory Addresses are mapped 1-1. I/O is mapped from 0 */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ +#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 |