Merge with git://www.denx.de/git/u-boot.git

1 files changed, 264 insertions, 120 deletions

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a0d291e..cda9fd5 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -11,7 +11,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -36,8 +36,14 @@
 #define CONFIG_MPC8548		1	/* MPC8548 specific */
 #define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
 
-#define CONFIG_PCI
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_PCI		/* enable any pci type devices */
+#define CONFIG_PCI1		/* PCI controller 1 */
+#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
+#undef CONFIG_RIO
+#undef CONFIG_PCI2
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
@@ -46,6 +52,7 @@
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 
 /*
@@ -65,16 +72,16 @@ extern unsigned long get_clock_freq(void);
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
-#define CONFIG_BTB			    /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
-
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
 #undef	CFG_DRAM_TEST			/* memory test, takes time */
@@ -85,10 +92,14 @@ extern unsigned long get_clock_freq(void);
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+#define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
+
 /*
  * DDR Setup
  */
@@ -106,7 +117,6 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */
@@ -124,9 +134,9 @@ extern unsigned long get_clock_freq(void);
  *    Use GPCM = BRx[24:26] = 000
  *    Valid = BRx[31] = 1
  *
- * 0    4    8    12   16   20   24   28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001	 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001	 BR1
  *
  * OR0, OR1:
  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
@@ -137,11 +147,12 @@ extern unsigned long get_clock_freq(void);
  *    TRLX = use relaxed timing = ORx[29] = 1
  *    EAD = use external address latch delay = OR[31] = 1
  *
- * 0    4    8    12   16   20   24   28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
  */
 
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+#define CFG_BOOT_BLOCK		0xff000000	/* boot TLB block */
+#define CFG_FLASH_BASE		CFG_BOOT_BLOCK	/* start of FLASH 16M */
 
 #define CFG_BR0_PRELIM		0xff801001
 #define CFG_BR1_PRELIM		0xff001001
@@ -156,7 +167,7 @@ extern unsigned long get_clock_freq(void);
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -166,7 +177,12 @@ extern unsigned long get_clock_freq(void);
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable */
+#define CFG_LBC_CACHE_SIZE	64
+#define CFG_LBC_NONCACHE_BASE	0xf8000000	/* Localbus non-cacheable */
+#define CFG_LBC_NONCACHE_SIZE	64
+
+#define CFG_LBC_SDRAM_BASE	CFG_LBC_CACHE_BASE	/* Localbus SDRAM */
 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
@@ -180,14 +196,14 @@ extern unsigned long get_clock_freq(void);
  *    SDRAM for MSEL = BR2[24:26] = 011
  *    Valid = BR[31] = 1
  *
- * 0    4    8    12   16   20   24   28
+ * 0	4    8	  12   16   20	 24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM          0xf0001861
+#define CFG_BR2_PRELIM		0xf0001861
 
 /*
  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
@@ -196,19 +212,19 @@ extern unsigned long get_clock_freq(void);
  *    64MB mask for AM, OR2[0:7] = 1111 1100
  *		   XAM, OR2[17:18] = 11
  *    9 columns OR2[19-21] = 010
- *    13 rows   OR2[23-25] = 100
+ *    13 rows	OR2[23-25] = 100
  *    EAD set for extra time OR[31] = 1
  *
- * 0    4    8    12   16   20   24   28
+ * 0	4    8	  12   16   20	 24   28
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
 #define CFG_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+#define CFG_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000	/* LB config reg */
+#define CFG_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
@@ -236,7 +252,7 @@ extern unsigned long get_clock_freq(void);
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
- *                  or BSMA1617 (for CPU 1.0) (old)
+ *		    or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
 #define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
@@ -256,61 +272,63 @@ extern unsigned long get_clock_freq(void);
  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  *    port-size = 8-bits  = BR[19:20] = 01
  *    no parity checking  = BR[21:22] = 00
- *    GPMC for MSEL       = BR[24:26] = 000
- *    Valid               = BR[31]    = 1
+ *    GPMC for MSEL	  = BR[24:26] = 000
+ *    Valid		  = BR[31]    = 1
  *
- * 0    4    8    12   16   20   24   28
+ * 0	4    8	  12   16   20	 24   28
  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  *
  * For OR3, need:
- *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    1 MB mask for AM,	  OR[0:16]  = 1111 1111 1111 0000 0
  *    disable buffer ctrl OR[19]    = 0
- *    CSNT                OR[20]    = 1
- *    ACS                 OR[21:22] = 11
- *    XACS                OR[23]    = 1
+ *    CSNT		  OR[20]    = 1
+ *    ACS		  OR[21:22] = 11
+ *    XACS		  OR[23]    = 1
  *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
- *    SETA                OR[28]    = 0
- *    TRLX                OR[29]    = 1
- *    EHTR                OR[30]    = 1
- *    EAD extra time      OR[31]    = 1
+ *    SETA		  OR[28]    = 0
+ *    TRLX		  OR[29]    = 1
+ *    EHTR		  OR[30]    = 1
+ *    EAD extra time	  OR[31]    = 1
  *
- * 0    4    8    12   16   20   24   28
+ * 0	4    8	  12   16   20	 24   28
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
 #define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM   0xf8000801
-#define CFG_OR3_PRELIM   0xfff00ff7
+#define CFG_BR3_PRELIM	 0xf8000801
+#define CFG_OR3_PRELIM	 0xfff00ff7
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
 
-#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
-#define CONFIG_CONS_INDEX     2
+#define CONFIG_CONS_INDEX	2
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_REG_SIZE	1
 #define CFG_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CFG_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
@@ -331,55 +349,74 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x57
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 #define CFG_I2C_OFFSET		0x3000
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
+#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CFG_PCI1_IO_BASE	0x00000000
 #define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00800000	/* 8M */
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
-#define CFG_PCI2_MEM_BASE	0x90000000
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
 #define CFG_PCI2_IO_BASE	0x00000000
 #define CFG_PCI2_IO_PHYS	0xe2800000
-#define CFG_PCI2_IO_SIZE	0x00800000	/* 8M */
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#endif
 
-#define CFG_PEX_MEM_BASE	0xa0000000
-#define CFG_PEX_MEM_PHYS	CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PEX_IO_BASE		0x00000000
-#define CFG_PEX_IO_PHYS		0xe3000000
-#define CFG_PEX_IO_SIZE		0x01000000	/* 16M */
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE	0xa0000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCIE1_IO_BASE	0x00000000
+#define CFG_PCIE1_IO_PHYS	0xe3000000
+#define CFG_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#endif
 
+#ifdef CONFIG_RIO
 /*
  * RapidIO MMU
  */
 #define CFG_RIO_MEM_BASE	0xC0000000
 #define CFG_RIO_MEM_SIZE	0x20000000	/* 512M */
+#endif
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
-#define CONFIG_85XX_PCI2
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
 
 #endif	/* CONFIG_PCI */
 
@@ -387,7 +424,7 @@ extern unsigned long get_clock_freq(void);
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -397,7 +434,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC2_NAME	"eTSEC1"
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC2"
-#undef CONFIG_TSEC4
+#define CONFIG_TSEC4
 #define CONFIG_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
@@ -413,7 +450,7 @@ extern unsigned long get_clock_freq(void);
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME		"eTSEC0"
-
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #endif	/* CONFIG_TSEC_ENET */
 
 /*
@@ -427,19 +464,28 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
 #if defined(CONFIG_PCI)
-#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
-				| CFG_CMD_PCI \
-				| CFG_CMD_PING \
-				| CFG_CMD_I2C \
-				| CFG_CMD_MII)
-#else
-#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
-				| CFG_CMD_PING \
-				| CFG_CMD_I2C \
-				| CFG_CMD_MII)
+    #define CONFIG_CMD_PCI
 #endif
-#include <cmd_confdefs.h>
+
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
@@ -449,7 +495,7 @@ extern unsigned long get_clock_freq(void);
 #define CFG_LONGHELP			/* undef to save memory	*/
 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
@@ -464,12 +510,12 @@ extern unsigned long get_clock_freq(void);
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /* Cache Configuration */
 #define CFG_DCACHE_SIZE	32768
 #define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 #endif
 
@@ -481,7 +527,7 @@ extern unsigned long get_clock_freq(void);
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
@@ -492,58 +538,156 @@ extern unsigned long get_clock_freq(void);
 
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_ETHADDR	 00:E0:0C:00:00:FD
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_ETH1ADDR	 00:E0:0C:00:01:FD
 #define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_ETH2ADDR	 00:E0:0C:00:02:FD
 #define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
+#define CONFIG_ETH3ADDR	 00:E0:0C:00:03:FD
 #endif
 
-#define CONFIG_IPADDR    192.168.1.253
+#define CONFIG_IPADDR	 192.168.1.253
 
-#define CONFIG_HOSTNAME  unknown
-#define CONFIG_ROOTPATH  /nfsroot
-#define CONFIG_BOOTFILE  your.uImage
+#define CONFIG_HOSTNAME	 unknown
+#define CONFIG_ROOTPATH	 /nfsroot
+#define CONFIG_BOOTFILE	8548cds/uImage.uboot
+#define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */
 
-#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_SERVERIP	 192.168.1.1
 #define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK   255.255.255.0
+#define CONFIG_NETMASK	 255.255.255.0
 
-#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
 
-#define	CONFIG_EXTRA_ENV_SETTINGS				        \
-   "netdev=eth0\0"                                                      \
-   "consoledev=ttyS1\0"                                                 \
-   "ramdiskaddr=600000\0"                                               \
-   "ramdiskfile=your.ramdisk.u-boot\0"					\
-   "fdtaddr=400000\0"							\
-   "fdtfile=your.fdt.dtb\0"
+#if defined(CONFIG_PCIE1)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
+	"pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
+	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
+	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
+#else
+#define	PCIE_ENV ""
+#endif
 
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+	"echo e;md ${a}e00 9\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
+	"pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
+#else
+#define	PCI_ENV ""
+#endif
 
-#define CONFIG_NFSBOOTCOMMAND	                                        \
-   "setenv bootargs root=/dev/nfs rw "                                  \
-      "nfsroot=$serverip:$rootpath "                                    \
+#if defined(CONFIG_PCI1)
+#define PCI_ENV1 \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
+#else
+#define	PCI_ENV1 ""
+#endif
+
+#if defined(CONFIG_PCI2)
+#define PCI_ENV2 \
+ "pci2regs=setenv a e0009; run pcireg\0" \
+ "pci2err=setenv a e0009; setenv b 123; run pcierr\0"	\
+ "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
+#else
+#define	PCI_ENV2 ""
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+	"md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+	"echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet2regs=setenv a e0025; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0" \
+ "enet4regs=setenv a e0027; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
+
+#if 0
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "netdev=eth0\0"						\
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+ "tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+ "consoledev=ttyS1\0"				\
+ "ramdiskaddr=2000000\0"			\
+ "ramdiskfile=ramdisk.uboot\0"			\
+ "dtbaddr=c00000\0"				\
+ "dtbfile=mpc8548cds.dtb\0"			\
+ "eoi=mw e00400b0 0\0"				\
+ "iack=md e00400a0 1\0"				\
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
+	"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0"		\
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+	"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0"	\
+ "guregs=setenv a e00e0; run gureg\0"		\
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
+ PCI_ENV1 \
+ PCI_ENV2 \
+ ENET_ENV
+#endif
+
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"						\
-   "bootm $loadaddr - $fdtaddr"
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $dtbaddr $dtbfile;"						\
+   "bootm $loadaddr - $dtbaddr"
 
 
 #define CONFIG_RAMBOOTCOMMAND \
-   "setenv bootargs root=/dev/ram rw "                                  \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $ramdiskaddr $ramdiskfile;"                                    \
-   "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr $ramdiskaddr"
-
-#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $dtbaddr $dtbfile;"						\
+   "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND
 
 #endif	/* __CONFIG_H */