diff options
| author | Matthew McClintock <msm@freescale.com> | 2006-06-28 10:46:13 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2006-08-09 13:50:56 -0500 |
| commit | bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452 (patch) | |
| tree | ce438a459d25fb3db9daca4e183aa7c62c02bc8a /include/configs/MPC8548CDS.h | |
| parent | c88f9fe66b64247e5b6a38410ba315ca25596d16 (diff) | |
| download | u-boot-imx-bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452.zip u-boot-imx-bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452.tar.gz u-boot-imx-bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452.tar.bz2 | |
* Added VIA configuration table
* Added support for PCI2 on CDS
Patch by Andy Fleming 17-Mar-2006
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/MPC8548CDS.h')
| -rw-r--r-- | include/configs/MPC8548CDS.h | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b1f8a19..37b518c 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC |