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authorebony.zhu@freescale.com <ebony.zhu@freescale.com>2006-12-18 16:25:15 +0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-04-23 19:58:27 -0500
commit39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09 (patch)
treedf783cf7d54f509c2202875f506c937509822947 /include/configs/MPC8548CDS.h
parent41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7 (diff)
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u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default
This patch disables MPC8548CDS 2T_TIMING for DDR by default. Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
Diffstat (limited to 'include/configs/MPC8548CDS.h')
-rw-r--r--include/configs/MPC8548CDS.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index bfd316c..687fe84 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -41,7 +41,7 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */