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author | Kim Phillips <kim.phillips@freescale.com> | 2009-01-21 18:38:51 -0600 |
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committer | Kim Phillips <kim.phillips@freescale.com> | 2009-01-21 18:38:51 -0600 |
commit | be4880ebe4355e8782be4af4b337a1b98dffcbe3 (patch) | |
tree | 8b699181073305221b95f338a2d9107ab1bbfa3f /include/configs/MPC8548CDS.h | |
parent | 633639587e3596f0dbf5e6247dd3faf80b1d9063 (diff) | |
parent | 72d15e705bc3983884105cb7755c7ba80e74a0a5 (diff) | |
download | u-boot-imx-be4880ebe4355e8782be4af4b337a1b98dffcbe3.zip u-boot-imx-be4880ebe4355e8782be4af4b337a1b98dffcbe3.tar.gz u-boot-imx-be4880ebe4355e8782be4af4b337a1b98dffcbe3.tar.bz2 |
Merge branch 'master' into next
Diffstat (limited to 'include/configs/MPC8548CDS.h')
-rw-r--r-- | include/configs/MPC8548CDS.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 083afba..e1bd45e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -69,7 +69,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* @@ -100,7 +99,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ @@ -303,7 +302,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR3_PRELIM 0xf8000801 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |