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authorBen Warren <biggerbadderben@gmail.com>2009-01-24 20:44:56 -0800
committerBen Warren <biggerbadderben@gmail.com>2009-01-24 20:44:56 -0800
commitef29884b2708a6cce3b77f4ccaeea193d4e02c22 (patch)
tree2f6a28872ab9f5de9fec7ac878b8801f5f536eec /include/configs/MPC8544DS.h
parent4cd8ed40615a7d741ef2f09ee53779ec6907b8a6 (diff)
parent8f86a3636ef88427f880610638e80991adc41896 (diff)
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Merge git://git.denx.de/u-boot into u-boot
Diffstat (limited to 'include/configs/MPC8544DS.h')
-rw-r--r--include/configs/MPC8544DS.h48
1 files changed, 29 insertions, 19 deletions
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b31c2bb..59cfde6 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -66,7 +66,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.
@@ -264,50 +263,61 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
+#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_MEM_BASE2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BASE2
+#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
#if defined(CONFIG_PCI)
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_PHYS
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
#define CONFIG_VIDEO
@@ -337,8 +347,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE
+ #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
+ #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif