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| author | Jon Loeliger <jdl@freescale.com> | 2008-03-17 15:48:18 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:50 -0500 |
| commit | aa11d85cf318b961e029fe50d68ca47d004bce93 (patch) | |
| tree | 30fb129452749c5a8ea5e817d8fd125986b85dc9 /include/configs/MPC8541CDS.h | |
| parent | 2b40edb10d81da7bba724edbccd7f53777112579 (diff) | |
| download | u-boot-imx-aa11d85cf318b961e029fe50d68ca47d004bce93.zip u-boot-imx-aa11d85cf318b961e029fe50d68ca47d004bce93.tar.gz u-boot-imx-aa11d85cf318b961e029fe50d68ca47d004bce93.tar.bz2 | |
FSL DDR: Convert MPC8541CDS to new DDR code.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8541CDS.h')
| -rw-r--r-- | include/configs/MPC8541CDS.h | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index d948d76..29dff32 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -40,12 +40,6 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -59,8 +53,6 @@ */ #define CONFIG_ASSUME_AMD_FLASH -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - #ifndef __ASSEMBLY__ extern unsigned long get_clock_freq(void); #endif @@ -85,13 +77,23 @@ extern unsigned long get_clock_freq(void); #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -/* - * DDR Setup - */ +/* DDR Setup */ +#define CONFIG_FSL_DDR1 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD +#undef CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* * Make sure required options are set @@ -102,7 +104,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -317,6 +318,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + /* * I2C */ |