* The PS/2 mux on the BMS2003 board needs 450 ms after power on

  before we can access it; add delay in case we are faster (with no
  CF card inserted)

* Cleanup of some init functions

* Make sure SCC Ethernet is always stopped by the time we boot Linux
  to avoid Linux crashes by early packets coming in.

* Accelerate flash accesses on LWMON board by using buffered writes

1 files changed, 74 insertions, 74 deletions

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 951d1fe..2f1bb48 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -31,21 +31,21 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE		1	    /* BOOKE 			*/
+#define CONFIG_BOOKE		1	    /* BOOKE			*/
 #define CONFIG_E500		1	    /* BOOKE e500 family	*/
 #define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
-#define CONFIG_MPC85xx_REV1	1	    /* MPC85xx Rev 1 Chip       */
-#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
+#define CONFIG_MPC85xx_REV1	1	    /* MPC85xx Rev 1 Chip	*/
+#define CONFIG_MPC8540		1	    /* MPC8540 specific		*/
 #define CONFIG_MPC8540ADS	1	    /* MPC8540ADS board specific*/
 
-#undef  CONFIG_PCI	         	    /* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		    /* tsec ethernet support  */
+#undef	CONFIG_PCI			    /* pci ethernet support	*/
+#define CONFIG_TSEC_ENET		    /* tsec ethernet support  */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#define CONFIG_SPD_EEPROM		    /* Use SPD EEPROM for DDR setup */
+#undef	CONFIG_DDR_ECC			    /* only for ECC DDR module */
 
 #if defined(CONFIG_MPC85xx_REV1)
-#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+#define CONFIG_DDR_DLL			    /* possible DLL fix needed */
 #endif
 
 /* Using Localbus SDRAM to emulate flash before we can program the flash,
@@ -53,24 +53,24 @@
  */
 #undef CONFIG_RAM_AS_FLASH
 
-#if !defined(CONFIG_PCI) 		    /* some PCI card is 33Mhz only */
+#if !defined(CONFIG_PCI)		    /* some PCI card is 33Mhz only */
 #define CONFIG_SYS_CLK_FREQ	66000000    /* sysclk for MPC85xx	*/
 #else
 #define CONFIG_SYS_CLK_FREQ	33000000    /* most pci cards are 33Mhz */
 #endif
 
-#if !defined(CONFIG_SPD_EEPROM)             /* manually set up DDR parameters */
+#if !defined(CONFIG_SPD_EEPROM)		    /* manually set up DDR parameters */
 #define CONFIG_DDR_SETTING
 #endif
 
 /* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
-#undef  CONFIG_BTB			    /* toggle branch predition */
-#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
+#undef	CONFIG_BTB			    /* toggle branch predition	*/
+#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
 
-#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
-#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
+#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
 #define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x00400000
 
@@ -82,13 +82,13 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
-#define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR 	*/
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE		128             /* DDR is now 128MB     */
+#define CFG_SDRAM_SIZE		128		/* DDR is now 128MB	*/
 
 #if defined(CONFIG_RAM_AS_FLASH)
 #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
@@ -98,44 +98,44 @@
 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE    	0xf8000000	/* start of FLASH  16M	*/
+#define CFG_FLASH_BASE		0xf8000000	/* start of FLASH  16M	*/
 #define CFG_BR0_PRELIM		0xf8001801	/* port size 32bit */
 #else /* Boot from real Flash */
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M    */
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M	 */
 #define CFG_BR0_PRELIM		0xff001801	/* port size 32bit	*/
 #endif
 
-#define	CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash		*/
+#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash		*/
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device	*/
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef	CFG_RAMBOOT
 #endif
 
 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
 
 #if defined(CONFIG_DDR_SETTING)
-#define CFG_DDR_CS0_BNDS        0x00000007      /* 0-128MB              */
-#define CFG_DDR_CS0_CONFIG      0x80000002
-#define CFG_DDR_TIMING_1        0x37344321
-#define CFG_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning*/
-#define CFG_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR*/
-#define CFG_DDR_MODE            0x00000062      /* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL        0x05200100      /* autocharge,no open page*/
+#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB		*/
+#define CFG_DDR_CS0_CONFIG	0x80000002
+#define CFG_DDR_TIMING_1	0x37344321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning*/
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR*/
+#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page*/
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
-#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
 #define CFG_OR2_PRELIM		0xfc006901
 #define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
 #define CFG_LBC_LBCR		0x00000000
@@ -148,52 +148,52 @@
 #define CFG_LBC_LSDMR_5		0x4061b723
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CFG_BR4_PRELIM		0xf8000801	/* 32KB, 8-bit wide for ADS config reg */
 #else
-#define CFG_BR4_PRELIM          0xfc000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CFG_BR4_PRELIM		0xfc000801	/* 32KB, 8-bit wide for ADS config reg */
 #endif
-#define CFG_OR4_PRELIM          0xffffe1f1
-#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
+#define CFG_OR4_PRELIM		0xffffe1f1
+#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR   	0x40000000 	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_REG_SIZE	1
 #define CFG_NS16550_CLK		get_bus_freq(0)
-#define CONFIG_BAUDRATE	 	115200
+#define CONFIG_BAUDRATE		115200
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 
 /* General PCI */
 #define CFG_PCI_MEM_BASE	0xe0000000
@@ -203,22 +203,22 @@
 #define CONFIG_NET_MULTI
 #undef CONFIG_EEPRO100
 #define CONFIG_TULIP
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
   #if !defined(CONFIG_PCI_PNP)
-  #define PCI_ENET0_IOADDR      0xe0000000
-  #define PCI_ENET0_MEMADDR     0xe0000000
-  #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+  #define PCI_ENET0_IOADDR	0xe0000000
+  #define PCI_ENET0_MEMADDR	0xe0000000
+  #define PCI_IDSEL_NUMBER	0x0c	/*slot0->3(IDSEL)=12->15*/
   #endif
-#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 #if defined(CONFIG_MPC85xx_REV1)	/* Errata PCI 8 */
   #define CFG_PCI_SUBSYS_DEVICEID 0x0003
 #else
   #define CFG_PCI_SUBSYS_DEVICEID 0x0008
 #endif
 #elif defined(CONFIG_TSEC_ENET)
-#define CONFIG_NET_MULTI 	1
-#define CONFIG_PHY_M88E1011      1       /* GigaBit Ether PHY    */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_M88E1011	 1	 /* GigaBit Ether PHY	 */
 #define CONFIG_MII		1	/* MII PHY management	*/
 #define CONFIG_PHY_ADDR		8	/* PHY address	*/
 #endif
@@ -232,7 +232,7 @@
   #else
   #define CFG_ENV_IS_IN_FLASH	1
   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CFG_ENV_SECT_SIZE	0x40000 /* 256K(one sector) for env */
   #endif
   #define CFG_ENV_SIZE		0x2000
 #else
@@ -242,10 +242,10 @@
 #define CFG_ENV_SIZE		0x2000
 #endif
 
-#define CONFIG_BOOTARGS	"root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
 /*#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"*/
 #define CONFIG_BOOTCOMMAND	"bootm 0xff300000 0xff700000"
-#define CONFIG_BOOTDELAY	3 	/* -1 disable autoboot */
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
@@ -274,7 +274,7 @@
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"MPC8540ADS=> "	/* Monitor Command Prompt	*/
+#define CFG_PROMPT	"MPC8540ADS=> " /* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -291,10 +291,10 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
 
 /* Cache Configuration */
-#define CFG_DCACHE_SIZE	32768
+#define CFG_DCACHE_SIZE 32768
 #define CFG_CACHELINE_SIZE	32
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
@@ -315,17 +315,17 @@
 
 /* NOTE: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR  00:01:af:07:9b:8a
-#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
-#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#define CONFIG_ETHADDR	00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR	 00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR	 00:01:af:07:9b:8c
 #endif
 
-#define CONFIG_SERVERIP         163.12.64.52
-#define CONFIG_IPADDR           10.82.0.105
-#define CONFIG_GATEWAYIP        10.82.1.254
-#define CONFIG_NETMASK          255.255.254.0
-#define CONFIG_HOSTNAME         MPC8560ADS_PILOT_003
-#define CONFIG_ROOTPATH         /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
-#define CONFIG_BOOTFILE         pImage
+#define CONFIG_SERVERIP		163.12.64.52
+#define CONFIG_IPADDR		10.82.0.105
+#define CONFIG_GATEWAYIP	10.82.1.254
+#define CONFIG_NETMASK		255.255.254.0
+#define CONFIG_HOSTNAME		MPC8560ADS_PILOT_003
+#define CONFIG_ROOTPATH		/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+#define CONFIG_BOOTFILE		pImage
 
 #endif	/* __CONFIG_H */