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| author | Wolfgang Denk <wd@denx.de> | 2008-10-27 22:31:32 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-27 22:31:32 +0100 |
| commit | f8030519bbe20b836f3939742b959cbadfaad51b (patch) | |
| tree | ae23fde6c7c196fca5fb62d6e30103974179d961 /include/configs/MPC8536DS.h | |
| parent | 5deb8022c3749faac30e9ad9694691e2442b5c93 (diff) | |
| parent | c2083e0e11a03ef8be2e9f0ed8720fdc20832f3e (diff) | |
| download | u-boot-imx-f8030519bbe20b836f3939742b959cbadfaad51b.zip u-boot-imx-f8030519bbe20b836f3939742b959cbadfaad51b.tar.gz u-boot-imx-f8030519bbe20b836f3939742b959cbadfaad51b.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include/configs/MPC8536DS.h')
| -rw-r--r-- | include/configs/MPC8536DS.h | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 38be10d..c4389cc 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -41,6 +41,7 @@ #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -134,14 +135,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 #define CONFIG_SYS_DDR_SBE 0x00010000 -/* FIXME: Not used in fixed_sdram function */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */ -#define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */ -#define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */ -#define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */ - /* Make sure required options are set */ #ifndef CONFIG_SPD_EEPROM #error ("CONFIG_SPD_EEPROM is required") @@ -314,11 +307,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */ -/* PCI view of System Memory */ -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000 - #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |