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| author | Joe Hershberger <joe.hershberger@ni.com> | 2011-10-11 23:57:29 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2011-11-03 18:27:55 -0500 |
| commit | 2fef402097866b4172d7a966a72397a5ccba5b10 (patch) | |
| tree | 14a4deb28cb562df7e19eec7f654dcbde38f8d20 /include/configs/MPC837XERDB.h | |
| parent | 72cd4087c9644812b0fff9440e88e986d259bf41 (diff) | |
| download | u-boot-imx-2fef402097866b4172d7a966a72397a5ccba5b10.zip u-boot-imx-2fef402097866b4172d7a966a72397a5ccba5b10.tar.gz u-boot-imx-2fef402097866b4172d7a966a72397a5ccba5b10.tar.bz2 | |
mpc83xx: Cleanup usage of DDR constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/configs/MPC837XERDB.h')
| -rw-r--r-- | include/configs/MPC837XERDB.h | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 371fff7..bf8a94d 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -165,9 +165,11 @@ * Manually set up DDR parameters */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ @@ -178,7 +180,6 @@ | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ /* 0x00260802 */ /* DDR400 */ #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ @@ -188,9 +189,15 @@ | (3 << TIMING_CFG1_WRREC_SHIFT) \ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3935d322 */ /* 0x3937d322 */ -#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x02984cc8 */ #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) @@ -198,12 +205,13 @@ #if defined(CONFIG_DDR_2T_TIMING) #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ - | SDRAM_CFG_2T_EN \ - | SDRAM_CFG_DBW_32) + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE \ + | SDRAM_CFG_2T_EN) + /* 0x43088000 */ #else #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) + | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ #endif #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ |