Merge git://git.denx.de/u-boot into x1

Conflicts:

	drivers/usb/usb_ohci.c

1 files changed, 160 insertions, 160 deletions

diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index b2e6b3b..a4f2862 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -44,14 +44,14 @@
 /*
  * Hardware Reset Configuration Word
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
 	HRCWL_CORE_TO_CSB_2X1 |\
 	HRCWL_CE_TO_PLL_1X15)
 
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCICKDRV_ENABLE |\
@@ -67,8 +67,8 @@
 /*
  * System IO Config
  */
-#define CFG_SICRH		0x00000000
-#define CFG_SICRL		0x40000000
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x40000000
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
@@ -76,18 +76,18 @@
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
-#define CFG_83XX_DDR_USES_CS0
+#define CONFIG_SYS_83XX_DDR_USES_CS0
 
 #define CONFIG_DDR_ECC		/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
@@ -95,7 +95,7 @@
 /*
  * DDRCDR - DDR Control Driver Register
  */
-#define CFG_DDRCDR_VALUE	0x80080001
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
 
 #undef CONFIG_SPD_EEPROM	/* Do not use SPD EEPROM for DDR setup */
 
@@ -103,19 +103,19 @@
  * Manually set up DDR parameters
  */
 #define CONFIG_DDR_II
-#define CFG_DDR_SIZE		256 /* MB */
-#define CFG_DDR_CS0_BNDS	0x0000000f
-#define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
+#define CONFIG_SYS_DDR_SIZE		256 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
 				 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
-#define CFG_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
-#define CFG_DDR_SDRAM_CFG2	0x00001000
-#define CFG_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CFG_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000
+#define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 				 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CFG_DDR_MODE		0x47800432
-#define CFG_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_MODE		0x47800432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
 
-#define CFG_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 				 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 				 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 				 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
@@ -124,7 +124,7 @@
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CFG_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
+#define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
 				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
@@ -133,7 +133,7 @@
 				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 
-#define CFG_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+#define CONFIG_SYS_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
@@ -141,119 +141,119 @@
 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 				 (0 << TIMING_CFG2_CPO_SHIFT))
 
-#define CFG_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000 /* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * The reserved memory
  */
-#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
-#define CFG_FLASH_BASE		0xFF800000 /* FLASH base address */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000 /* FLASH base address */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_SIZE		8 /* max FLASH size is 32M */
-#define CFG_FLASH_PROTECTION	1 /* Use intel Flash protection. */
+#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use intel Flash protection. */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
 
-#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | /* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 			BR_V)	/* valid */
-#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
-#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 
-#undef	CFG_FLASH_CHECKSUM
+#undef	CONFIG_SYS_FLASH_CHECKSUM
 
 /*
  * NAND flash on the local bus
  */
-#define CFG_NAND_BASE		0x60000000
+#define CONFIG_SYS_NAND_BASE		0x60000000
 #define CONFIG_CMD_NAND		1
 #define CONFIG_NAND_FSL_UPM	1
-#define CFG_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
-#define CFG_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */
 
 /* Port size 8 bit, UPMA */
-#define CFG_BR1_PRELIM		(CFG_NAND_BASE | 0x00000881)
-#define CFG_OR1_PRELIM		0xfc000001
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_NAND_BASE | 0x00000881)
+#define CONFIG_SYS_OR1_PRELIM		0xfc000001
 
 /*
  * Fujitsu MB86277 (MINT) graphics controller
  */
-#define CFG_VIDEO_BASE		0x70000000
+#define CONFIG_SYS_VIDEO_BASE		0x70000000
 
-#define CFG_LBLAWBAR2_PRELIM	CFG_VIDEO_BASE
-#define CFG_LBLAWAR2_PRELIM	0x80000019 /* Access window size 64MB */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VIDEO_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* Access window size 64MB */
 
 /* Port size 32 bit, UPMB */
-#define CFG_BR2_PRELIM		(CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
-#define CFG_OR2_PRELIM		0xfc000001 /* (64MB, EAD=1) */
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
+#define CONFIG_SYS_OR2_PRELIM		0xfc000001 /* (64MB, EAD=1) */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* Pass open firmware flat tree */
@@ -267,11 +267,11 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE	0x7F
-#define CFG_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET	0x3000
-#define CFG_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
 
 /*
  * General PCI
@@ -280,15 +280,15 @@
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI	1
 
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000 /* 256M */
-#define CFG_PCI1_MMIO_BASE	0x90000000
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI1_IO_BASE	0xE0300000
-#define CFG_PCI1_IO_PHYS	0xE0300000
-#define CFG_PCI1_IO_SIZE	0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0xE0300000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000 /* 1M */
 
 #ifdef CONFIG_PCI
 
@@ -297,7 +297,7 @@
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -315,43 +315,43 @@
 #define CONFIG_UEC_ETH1		/* GETH1 */
 
 #ifdef CONFIG_UEC_ETH1
-#define CFG_UEC1_UCC_NUM	0	/* UCC1 */
-#define CFG_UEC1_RX_CLK		QE_CLK_NONE
-#define CFG_UEC1_TX_CLK		QE_CLK9
-#define CFG_UEC1_ETH_TYPE	GIGA_ETH
-#define CFG_UEC1_PHY_ADDR	2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	2
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
 
 #ifdef CONFIG_UEC_ETH2
-#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
-#define CFG_UEC2_RX_CLK		QE_CLK_NONE
-#define CFG_UEC2_TX_CLK		QE_CLK4
-#define CFG_UEC2_ETH_TYPE	GIGA_ETH
-#define CFG_UEC2_PHY_ADDR	4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
+#define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	4
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 /*
  * Environment
  */
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x20000
-#else /* CFG_RAMBOOT */
-#define CFG_NO_FLASH		1	/* Flash is not usable now */
+#else /* CONFIG_SYS_RAMBOOT */
+#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -376,7 +376,7 @@
 #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 #undef CONFIG_CMD_ENV
 #undef CONFIG_CMD_LOADS
 #endif
@@ -386,34 +386,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000 /* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -422,65 +422,65 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* NAND: cache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 			 BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT4L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT4U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
-#define CFG_IBAT5L	(CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
 			 BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else /* CONFIG_PCI */
-#define CFG_IBAT6L	(0)
-#define CFG_IBAT6U	(0)
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif /* CONFIG_PCI */
 
 /*