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| author | Joe Hershberger <joe.hershberger@ni.com> | 2011-10-11 23:57:31 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2011-11-03 18:27:56 -0500 |
| commit | 2e651b248348e156d193e46f7a5b827d74af90d6 (patch) | |
| tree | 76515fcf8008dbaefcdfdb6afffdb79376a82057 /include/configs/MPC8360EMDS.h | |
| parent | 7d6a098219f8473ca4653cce5f7a49672b967f36 (diff) | |
| download | u-boot-imx-2e651b248348e156d193e46f7a5b827d74af90d6.zip u-boot-imx-2e651b248348e156d193e46f7a5b827d74af90d6.tar.gz u-boot-imx-2e651b248348e156d193e46f7a5b827d74af90d6.tar.bz2 | |
mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code
Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
Cleanup the setting of the csnbds to respect the setting of
CONFIG_SYS_DDR_SDRAM_BASE
Use __ilog2 instead of writing the code to compute it
Disable unused CS configs
Ensure ddrlaw.bar is configured
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/configs/MPC8360EMDS.h')
| -rw-r--r-- | include/configs/MPC8360EMDS.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index aaff93f..e81f3d4 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -145,9 +145,10 @@ #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_9) +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_9) +#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ |