Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 188 insertions, 188 deletions

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 81ea9f8..f633f24 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -57,7 +57,7 @@
 #define __CONFIG_H
 
 #if (TEXT_BASE == 0xFE000000)
-#define CFG_LOWBOOT
+#define CONFIG_SYS_LOWBOOT
 #endif
 
 /*
@@ -66,7 +66,7 @@
 #define CONFIG_MPC834X		/* MPC834x family (8343, 8347, 8349) */
 #define CONFIG_MPC8349		/* MPC8349 specific */
 
-#define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
+#define CONFIG_SYS_IMMR		0xE0000000	/* The IMMR is relocated to here */
 
 #define CONFIG_MISC_INIT_F
 #define CONFIG_MISC_INIT_R
@@ -95,26 +95,26 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
-#define CFG_SPD_BUS_NUM		1	/* The I2C bus for SPD */
-
-#define CFG_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
-#define CFG_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
-#define CFG_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
-#define CFG_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
-#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
-#define CFG_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
+
+#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
 #define SPD_EEPROM_ADDRESS	0x51	/* I2C1, DDR */
 
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /* Don't probe these addresses: */
-#define CFG_I2C_NOPROBES	{{1, CFG_I2C_8574_ADDR1}, \
-				 {1, CFG_I2C_8574_ADDR2}, \
-				 {1, CFG_I2C_8574A_ADDR1}, \
-				 {1, CFG_I2C_8574A_ADDR2}}
+#define CONFIG_SYS_I2C_NOPROBES	{{1, CONFIG_SYS_I2C_8574_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR2}}
 /* Bit definitions for the 8574[A] I2C expander */
 #define I2C_8574_REVISION	0x03	/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 #define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
@@ -129,15 +129,15 @@
 /* Compact Flash */
 #ifdef CONFIG_COMPACT_FLASH
 
-#define CFG_IDE_MAXBUS		1
-#define CFG_IDE_MAXDEVICE	1
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_BASE_ADDR	CFG_CF_BASE
-#define CFG_ATA_DATA_OFFSET	0x0000
-#define CFG_ATA_REG_OFFSET	0
-#define CFG_ATA_ALT_OFFSET	0x0200
-#define CFG_ATA_STRIDE		2
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
+#define CONFIG_SYS_ATA_STRIDE		2
 
 #define ATA_RESET_TIME	1	/* If a CF card is not inserted, time out quickly */
 
@@ -148,14 +148,14 @@
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_83XX_DDR_USES_CS0
-#define CFG_MEMTEST_START	0x1000		/* memtest region */
-#define CFG_MEMTEST_END		0x2000
-
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+#define CONFIG_SYS_MEMTEST_START	0x1000		/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x2000
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 
 #ifdef CONFIG_HARD_I2C
@@ -163,34 +163,34 @@
 #endif
 
 #ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
-    #define CFG_DDR_SIZE	256		/* Mb */
-    #define CFG_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+    #define CONFIG_SYS_DDR_SIZE	256		/* Mb */
+    #define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 
-    #define CFG_DDR_TIMING_1	0x26242321
-    #define CFG_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
+    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
+    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
 #endif
 
 /*
  *Flash on the Local Bus
  */
 
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 
 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 boards, we say we have two, but don't display a message if we find only one. */
-#define CFG_FLASH_QUIET_TEST
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
-#define CFG_FLASH_SIZE		16		/* FLASH size in MB */
-#define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
-#define CFG_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
+#define CONFIG_SYS_FLASH_SIZE		16		/* FLASH size in MB */
+#define CONFIG_SYS_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 
 /* Vitesse 7385 */
 
@@ -210,34 +210,34 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* Flash */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_V)
-#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE
-#define CFG_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
 
 /* Vitesse 7385 */
 
-#define CFG_VSC7385_BASE	0xF8000000
+#define CONFIG_SYS_VSC7385_BASE	0xF8000000
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
-#define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CFG_LBLAWBAR1_PRELIM	CFG_VSC7385_BASE
-#define CFG_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_VSC7385_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
 
 #endif
 
 /* LED */
 
-#define CFG_LED_BASE		0xF9000000
-#define CFG_BR2_PRELIM		(CFG_LED_BASE | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+#define CONFIG_SYS_LED_BASE		0xF9000000
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)
 
@@ -245,39 +245,39 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #ifdef CONFIG_COMPACT_FLASH
 
-#define CFG_CF_BASE		0xF0000000
+#define CONFIG_SYS_CF_BASE		0xF0000000
 
-#define CFG_BR3_PRELIM		(CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
-#define CFG_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
+#define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
 
-#define CFG_LBLAWBAR3_PRELIM	CFG_CF_BASE
-#define CFG_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
 
 #endif
 
 /*
  * U-Boot memory configuration
  */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
@@ -285,30 +285,30 @@ boards, we say we have two, but don't display a message if we find only one. */
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR	0x00000000
+#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR	0x00000000
 
-#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
+#define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_CONSOLE		ttyS0
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -326,26 +326,26 @@ boards, we say we have two, but don't display a message if we find only one. */
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_MMIO_BASE	(CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xE2000000
-#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M */
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CFG_PCI2_MEM_BASE	(CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE)
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_MMIO_BASE	(CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE)
-#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
-#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	(CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE)
-#define CFG_PCI2_IO_SIZE	0x01000000	/* 16M */
+#define CONFIG_SYS_PCI2_MEM_BASE	(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_SIZE	0x01000000	/* 16M */
 #endif
 
 #define _IO_BASE		0x00000000	/* points to PCI I/O space */
@@ -360,7 +360,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #ifndef CONFIG_PCI_PNP
     #define PCI_ENET0_IOADDR	0x00000000
-    #define PCI_ENET0_MEMADDR	CFG_PCI2_MEM_BASE
+    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
     #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
 #endif
 
@@ -388,7 +388,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME  "TSEC0"
-#define CFG_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
 #define TSEC1_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
@@ -397,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
-#define CFG_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
 
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_PHYIDX		0
@@ -413,21 +413,21 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
   #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
   #define CONFIG_ENV_SIZE		0x2000
 #else
-  #define CFG_NO_FLASH		/* Flash is not usable now */
+  #define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
   #undef  CONFIG_FLASH_CFI_DRIVER
   #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -469,47 +469,47 @@ boards, we say we have two, but don't display a message if we find only one. */
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_HUSH_PARSER			/* Use the HUSH parser */
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_LOADADDR	500000	/* default location for tftp and bootm */
 
 #ifdef CONFIG_MPC8349ITX
-#define CFG_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_4X1 |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 
-#ifdef CFG_LOWBOOT
-#define CFG_HRCW_HIGH (\
+#ifdef CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -522,7 +522,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -539,81 +539,81 @@ boards, we say we have two, but don't display a message if we find only one. */
 /*
  * System performance
  */
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
-#define CFG_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CFG_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
-#define CFG_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
-#define CFG_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 
 /*
  * System IO Config
  */
-#define CFG_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
-#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
+#define CONFIG_SYS_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
+#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	CFG_HID0_INIT
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT
 
-#define CFG_HID2	HID2_HBE
+#define CONFIG_SYS_HID2	HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR  */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI  */
 #ifdef CONFIG_PCI
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT1L	0
-#define CFG_IBAT1U	0
-#define CFG_IBAT2L	0
-#define CFG_IBAT2U	0
+#define CONFIG_SYS_IBAT1L	0
+#define CONFIG_SYS_IBAT1U	0
+#define CONFIG_SYS_IBAT2L	0
+#define CONFIG_SYS_IBAT2U	0
 #endif
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT3L	0
-#define CFG_IBAT3U	0
-#define CFG_IBAT4L	0
-#define CFG_IBAT4U	0
+#define CONFIG_SYS_IBAT3L	0
+#define CONFIG_SYS_IBAT3U	0
+#define CONFIG_SYS_IBAT4L	0
+#define CONFIG_SYS_IBAT4U	0
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT7L	0
-#define CFG_IBAT7U	0
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions