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authorLee Nipper <lee.nipper@freescale.com>2008-04-25 15:44:45 -0500
committerKim Phillips <kim.phillips@freescale.com>2008-05-06 13:22:25 -0500
commita5fe514e8ace564300d2c1d73846ddff49654243 (patch)
treea5338dbec705f366c023f3a18c0fc73ba9613676 /include/configs/MPC8349EMDS.h
parent908261f3fdb418091d8c60bfbd7eb85e5869b579 (diff)
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mpc83xx: system performance settings for MPC8349EMDS.
These same settings are used on MPC8349ITX, and improve performance on MPC8349EMDS. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/configs/MPC8349EMDS.h')
-rw-r--r--include/configs/MPC8349EMDS.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 364ffac..cf552c2 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -602,6 +602,16 @@
HRCWH_TSEC2M_IN_GMII )
#endif
+/*
+ * System performance
+ */
+#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
+#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
+#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
+#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
+
/* System IO Config */
#define CFG_SICRH SICRH_TSOBI1
#define CFG_SICRL SICRL_LDP_A