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| author | Kim Phillips <kim.phillips@freescale.com> | 2009-06-05 14:11:33 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-06-08 10:45:09 -0500 |
| commit | 3c9b1ee17e19bd6d80344678d41a85e52b0be713 (patch) | |
| tree | a319178aa16dbe1e083a6ff2b99c5cd71207c18d /include/configs/MPC8349EMDS.h | |
| parent | 3bc8556f9b24af60dba2b55a0abb1182dff45ecc (diff) | |
| download | u-boot-imx-3c9b1ee17e19bd6d80344678d41a85e52b0be713.zip u-boot-imx-3c9b1ee17e19bd6d80344678d41a85e52b0be713.tar.gz u-boot-imx-3c9b1ee17e19bd6d80344678d41a85e52b0be713.tar.bz2 | |
mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation
In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer
impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0.
SICRH[TSIOB1] was erroneously being set high.
U-Boot always operated this PHY interface in GMII mode. It is assumed this
was missed in the clean up by the original board porters, and copied along
to the TQM and sbc boards.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Ira Snyder <iws@ovro.caltech.edu>
Reviewed-by: David Hawkins <dwh@ovro.caltech.edu>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: Dave Liu <DaveLiu@freescale.com>
Diffstat (limited to 'include/configs/MPC8349EMDS.h')
| -rw-r--r-- | include/configs/MPC8349EMDS.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3c57403..2d2799e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -598,7 +598,7 @@ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 |