mpc83xx: Cleanup usage of LBC constants

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

1 files changed, 63 insertions, 80 deletions

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index d552046..4ed5a97 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -210,12 +210,22 @@
 
 					/* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
 
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| (2 << BR_PS_SHIFT)	/* 16 bit port */ \
-				| BR_V)			/* valid */
-#define CONFIG_SYS_OR0_PRELIM	0xfe006ff7		/* 16MB Flash size */
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xfe006ff7 */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
@@ -228,94 +238,67 @@
 #define CONFIG_SYS_BCSR			0xF8000000
 					/* Access window base at BCSR base */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
-					/* Access window size 32K */
-#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E
-
-					/* Port size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)
-#define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7	/* length 32K */
-
-/*
- * SDRAM on the Local Bus
- */
-#undef CONFIG_SYS_LB_SDRAM	/* The board has not SRDAM on local bus */
-
-#ifdef CONFIG_SYS_LB_SDRAM
-#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
-#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
-
-/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- *    port size = 32-bits = BR2[19:20] = 11
- *    no parity checking = BR2[21:22] = 00
- *    SDRAM for MSEL = BR2[24:26] = 011
- *    Valid = BR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * the top 17 bits of BR2.
- */
-
-#define CONFIG_SYS_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- *    64MB mask for AM, OR2[0:7] = 1111 1100
- *                 XAM, OR2[17:18] = 11
- *    9 columns OR2[19-21] = 010
- *    13 rows   OR2[23-25] = 100
- *    EAD set for extra time OR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM	0xfc006901
-
-				/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT	0x32000000
-				/* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR	0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
-
-#endif
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
+					| BR_PS_8 \
+					| BR_MS_GPCM \
+					| BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
+					| OR_GPCM_XAM \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xFFFFE9F7 */
 
 /*
  * Windows to access PIB via local bus
  */
-					/* windows base 0xf8008000 */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8008000
-					/* windows size 64KB */
-#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000f
+					/* PIB window base 0xF8008000 */
+#define CONFIG_SYS_PIB_BASE		0xF8008000
+#define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PIB_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
 
 /*
  * CS2 on Local Bus, to PIB
  */
-				/* CS2 base address at 0xf8008000 */
-#define CONFIG_SYS_BR2_PRELIM	0xf8008801
-				/* size 32KB, port size 8bit, GPCM */
-#define CONFIG_SYS_OR2_PRELIM	0xffffe9f7
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_PIB_BASE \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+				/* 0xF8008801 */
+#define CONFIG_SYS_OR2_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xffffe9f7 */
 
 /*
  * CS3 on Local Bus, to PIB
  */
-				/* CS3 base address at 0xf8010000 */
-#define CONFIG_SYS_BR3_PRELIM	0xf8010801
-				/* size 32KB, port size 8bit, GPCM */
-#define CONFIG_SYS_OR3_PRELIM	0xffffe9f7
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIB_BASE + \
+					CONFIG_SYS_PIB_WINDOW_SIZE) \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+				/* 0xF8010801 */
+#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xffffe9f7 */
 
 /*
  * Serial Port