Merge git://git.denx.de/u-boot into x1

Conflicts:

	drivers/usb/usb_ohci.c

1 files changed, 117 insertions, 117 deletions

diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 26c6fbe..fe1cc17 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -36,7 +36,7 @@
    !!  To make it work for the default, the TEXT_BASE define in	      !!
    !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
    !!  0xfff00000						      !!
-   !!  The CFG_HRCW_MASTER define below must also be changed to match !!
+   !!  The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
    !!								      !!
    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  */
@@ -115,18 +115,18 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Half duplex
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif	/* CONFIG_ETHER_INDEX */
 
 /* other options */
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
 /* PCI */
 #define CONFIG_PCI
@@ -218,47 +218,47 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16			/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
 #undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
 					/* for versions < 2.4.5-pre5	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
 #define FLASH_BASE		0xFE000000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
-#define CFG_FLASH_SIZE		8
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
 
-#undef	CFG_FLASH_CHECKSUM
+#undef	CONFIG_SYS_FLASH_CHECKSUM
 
 /* this is stuff came out of the Motorola docs */
 /* Only change this if you also change the Hardware configuration Word */
-#define CFG_DEFAULT_IMMR	0x0F010000
+#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
 
 /* Set IMMR to 0xF0000000 or above to boot Linux  */
-#define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0xF8000000
-#define CFG_PCI_INT		0xF8200000	/* PCI interrupt controller */
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_BCSR		0xF8000000
+#define CONFIG_SYS_PCI_INT		0xF8200000	/* PCI interrupt controller */
 
 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
  */
@@ -267,8 +267,8 @@
 /* What should be the base address of SDRAM DIMM and how big is
  * it (in Mbytes)?  This will normally auto-configure via the SPD.
 */
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 16
 
 #define SDRAM_SPD_ADDR 0x50
 
@@ -295,12 +295,12 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_BR3_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
@@ -314,13 +314,13 @@
  *     - Back-to-back page mode
  *     - Internal bank interleaving within save device enabled
  */
-#if (CFG_SDRAM_SIZE == 64)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM_SIZE)	|\
+#if (CONFIG_SYS_SDRAM_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)	|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A8		|\
 			 ORxS_NUMR_12)
-#elif (CFG_SDRAM_SIZE == 16)
-#define CFG_OR2_PRELIM	(0xFF000C80)
+#elif (CONFIG_SYS_SDRAM_SIZE == 16)
+#define CONFIG_SYS_OR2_PRELIM	(0xFF000C80)
 #else
 #error "INVALID SDRAM CONFIGURATION"
 #endif
@@ -331,7 +331,7 @@
  *-----------------------------------------------------------------------
  */
 
-#if (CFG_SDRAM_SIZE == 64)
+#if (CONFIG_SYS_SDRAM_SIZE == 64)
 /* With a 64 MB DIMM, the PSDMR is configured as follows:
  *
  *     - Bank Based Interleaving,
@@ -349,7 +349,7 @@
  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
  *     - CAS Latency is 2.
  */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
 			 PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A14_A16   |\
 			 PSDMR_SDA10_PBI0_A9  |\
@@ -359,12 +359,12 @@
 			 PSDMR_LDOTOPRE_1C    |\
 			 PSDMR_WRC_1C	      |\
 			 PSDMR_CL_2)
-#elif (CFG_SDRAM_SIZE == 16)
+#elif (CONFIG_SYS_SDRAM_SIZE == 16)
 /* With a 16 MB DIMM, the PSDMR is configured as follows:
  *
  *   configuration parameters found in Motorola documentation
  */
-#define CFG_PSDMR	(0x016EB452)
+#define CONFIG_SYS_PSDMR	(0x016EB452)
 #else
 #error "INVALID SDRAM CONFIGURATION"
 #endif
@@ -374,22 +374,22 @@
 #define FETHIEN			0x08000008
 #define FETH_RST		0x04000004
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
 /* 0x0EB2B645 */
-#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
+#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
 			 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )		|\
 			 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )	|\
 			 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )			\
 			)
 
 /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
-/* #define CFG_HRCW_MASTER 0x0cb23645 */
+/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
 
 /* This value should actually be situated in the first 256 bytes of the FLASH
 	which on the standard MPC8266ADS board is at address 0xFF800000
@@ -406,39 +406,39 @@
 */
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
 
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM	0x02	/* Software reboot	     */
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #  define CONFIG_ENV_IS_IN_FLASH	1
-#    define CONFIG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #    define CONFIG_ENV_SECT_SIZE	0x40000
 #else
 #  define CONFIG_ENV_IS_IN_NVRAM	1
-#  define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #  define CONFIG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -451,22 +451,22 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-/*#define CFG_HID0_INIT		0 */
-#define CFG_HID0_INIT	(HID0_ICE  |\
+/*#define CONFIG_SYS_HID0_INIT		0 */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
 			 HID0_DCE  |\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
 
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x004C0000
-#define CFG_SIUMCR		0x4E64C000
-#define CFG_SCCR		0x00000000
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x004C0000
+#define CONFIG_SYS_SIUMCR		0x4E64C000
+#define CONFIG_SYS_SCCR		0x00000000
 
 /*	local bus memory map
  *
@@ -481,31 +481,31 @@
  *	0xF8300000-0xF8307FFF	 32KB	EEPROM
  *	0xFE000000-0xFFFFFFFF	 32MB	flash
  */
-#define CFG_BR0_PRELIM	0xFE001801		/* flash */
-#define CFG_OR0_PRELIM	0xFE000836
-#define CFG_BR1_PRELIM	(CFG_BCSR | 0x1801)	/* BCSR */
-#define CFG_OR1_PRELIM	0xFFFF8010
-#define CFG_BR4_PRELIM	0xF8300801		/* EEPROM */
-#define CFG_OR4_PRELIM	0xFFFF8846
-#define CFG_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
-#define CFG_OR5_PRELIM	0xFFFF8E36
-#define CFG_BR8_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
-#define CFG_OR8_PRELIM	0xFFFF8010
-
-#define CFG_RMR			0x0001
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
-#define CFG_MPTPR		0x00001900
-#define CFG_PSRT		0x00000021
+#define CONFIG_SYS_BR0_PRELIM	0xFE001801		/* flash */
+#define CONFIG_SYS_OR0_PRELIM	0xFE000836
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR | 0x1801)	/* BCSR */
+#define CONFIG_SYS_OR1_PRELIM	0xFFFF8010
+#define CONFIG_SYS_BR4_PRELIM	0xF8300801		/* EEPROM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFF8846
+#define CONFIG_SYS_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
+#define CONFIG_SYS_OR5_PRELIM	0xFFFF8E36
+#define CONFIG_SYS_BR8_PRELIM	(CONFIG_SYS_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CONFIG_SYS_OR8_PRELIM	0xFFFF8010
+
+#define CONFIG_SYS_RMR			0x0001
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+#define CONFIG_SYS_MPTPR		0x00001900
+#define CONFIG_SYS_PSRT		0x00000021
 
 /* This address must not exist */
-#define CFG_RESET_ADDRESS	0xFCFFFF00
+#define CONFIG_SYS_RESET_ADDRESS	0xFCFFFF00
 
 /* PCI Memory map (if different from default map */
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
-#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
 				 PICMR_PREFETCH_EN)
 
 /*
@@ -516,11 +516,11 @@
  */
 
 /* PCIBR0 */
-#define CFG_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
-#define CFG_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
 /* PCIBR1 */
-#define CFG_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
-#define CFG_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#define CONFIG_SYS_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
 
 /*
  * Master window that allows the CPU to access PCI Memory (prefetch).
@@ -528,11 +528,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000			/* Local base */
-#define CFG_PCI_MSTR_MEM_BUS	0x80000000			/* PCI base   */
-#define CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE	0x20000000			/* 512MB */
-#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000			/* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 
 /*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
@@ -540,11 +540,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000			/* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS	    0xA0000000			/* PCI base   */
-#define CFG_CPU_PCI_MEMIO_START	    PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE	    0x20000000			/* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB	    (POCMR_MASK_512MB | POCMR_ENABLE)
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS	    0xA0000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START	    PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE	    0x20000000			/* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB	    (POCMR_MASK_512MB | POCMR_ENABLE)
 
 /*
  * Master window that allows the CPU to access PCI IO space.
@@ -552,11 +552,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_IO_LOCAL	    0xF4000000			/* Local base */
-#define CFG_PCI_MSTR_IO_BUS	    0xF4000000			/* PCI base   */
-#define CFG_CPU_PCI_IO_START	    PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE	    0x04000000			/* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB	    (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL	    0xF4000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS	    0xF4000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START	    PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE	    0x04000000			/* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB	    (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
 
 /*
  * JFFS2 partitions