Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

1 files changed, 75 insertions, 75 deletions

diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index dde7742..8e7f9cd 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -63,7 +63,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
@@ -89,14 +89,14 @@
 			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xFE
-#define CFG_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
+#define CONFIG_SYS_I2C_SPEED			50000
+#define CONFIG_SYS_I2C_SLAVE			0xFE
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 #define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
 #define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
@@ -142,25 +142,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x300000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -171,29 +171,29 @@
 /*-----------------------------------------------------------------------
  * Physical memory map
  */
-#define CFG_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
+#define CONFIG_SYS_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xfe000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
 
-#define CFG_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
-#undef	CFG_MONITOR_BASE		    /* to run U-Boot from RAM */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
+#undef	CONFIG_SYS_MONITOR_BASE		    /* to run U-Boot from RAM */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * JFFS2 partitions
@@ -218,26 +218,26 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		CFG_MONITOR_LEN /* Offset of Environment */
-#define CFG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
+#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -247,10 +247,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWP)
 #endif
 
@@ -259,27 +259,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_SEME)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_SEME)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		12-18
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -290,7 +290,7 @@
 #define MPC8XX_SPEED	50000000L
 #define MPC8XX_XIN	5000000L      /* ref clk */
 #define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -301,7 +301,7 @@
  */
 
 #define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
-#define CFG_SCCR	(SCCR_TBS | SCCR_DFLCD001)
+#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_DFLCD001)
 
 
 /*-----------------------------------------------------------------------
@@ -310,8 +310,8 @@
  *-----------------------------------------------------------------------
  * periodic timer for refresh
  */
-#define CFG_MAMR_PTA	0xC0
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
+#define CONFIG_SYS_MAMR_PTA	0xC0
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
 
 /*
  * BR0 and OR0 (FLASH) used to re-map FLASH
@@ -320,14 +320,14 @@
 /* allow for max 8 MB of Flash */
 #define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
 #define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
-#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -337,46 +337,46 @@
 #define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
 
 /* SDRAM timing: drive GPL5 high on first cycle */
-#define CFG_OR_TIMING_SDRAM	(OR_G5LS)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS)
 
-#define CFG_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR2/OR2 - DIMM
  */
-#define CFG_OR2		(OR_ACS_DIV4)
-#define CFG_BR2		(BR_MS_UPMA)
+#define CONFIG_SYS_OR2		(OR_ACS_DIV4)
+#define CONFIG_SYS_BR2		(BR_MS_UPMA)
 
 /*
  * BR3/OR3 - DIMM
  */
-#define CFG_OR3		(OR_ACS_DIV4)
-#define CFG_BR3		(BR_MS_UPMA)
+#define CONFIG_SYS_OR3		(OR_ACS_DIV4)
+#define CONFIG_SYS_BR3		(BR_MS_UPMA)
 
 /*
  * BR4/OR4
  */
-#define CFG_OR4		0
-#define CFG_BR4		0
+#define CONFIG_SYS_OR4		0
+#define CONFIG_SYS_BR4		0
 
 /*
  * BR5/OR5
  */
-#define CFG_OR5		0
-#define CFG_BR5		0
+#define CONFIG_SYS_OR5		0
+#define CONFIG_SYS_BR5		0
 
 /*
  * BR6/OR6
  */
-#define CFG_OR6		0
-#define CFG_BR6		0
+#define CONFIG_SYS_OR6		0
+#define CONFIG_SYS_BR6		0
 
 /*
  * BR7/OR7
  */
-#define CFG_OR7		0
-#define CFG_BR7		0
+#define CONFIG_SYS_OR7		0
+#define CONFIG_SYS_BR7		0
 
 
 /*-----------------------------------------------------------------------
@@ -384,7 +384,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Internal Definitions