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| author | Wolfgang Denk <wd@denx.de> | 2010-03-28 00:04:18 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-03-28 00:04:18 +0100 |
| commit | be1a91320ce0cb7330bb650d1576bb56c55092af (patch) | |
| tree | f6bb6d34565d4f5b3386a23885fb3df6c17e0456 /include/configs/M53017EVB.h | |
| parent | 6b94b4962211c16ee2197048faa887e1f92f3757 (diff) | |
| parent | 9d3a86aec52cb3c0e9badd12167d9292184ce4dd (diff) | |
| download | u-boot-imx-be1a91320ce0cb7330bb650d1576bb56c55092af.zip u-boot-imx-be1a91320ce0cb7330bb650d1576bb56c55092af.tar.gz u-boot-imx-be1a91320ce0cb7330bb650d1576bb56c55092af.tar.bz2 | |
Merge branch 'next' of git://git.denx.de/u-boot-coldfire into next
Diffstat (limited to 'include/configs/M53017EVB.h')
| -rw-r--r-- | include/configs/M53017EVB.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 30855bd..d983a8f 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -69,6 +69,8 @@ # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_TX_ETH_BUFFER 8 +# define CONFIG_SYS_FEC_BUF_USE_SRAM # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_HAS_ETH1 @@ -166,7 +168,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET @@ -180,7 +182,7 @@ #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 @@ -231,6 +233,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ |