Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 61 insertions, 61 deletions

diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index b0ef41e..1f3539e 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -44,9 +44,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -90,22 +90,22 @@
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
-#define CFG_DISCOVER_PHY
-#define CFG_RX_ETH_BUFFER	8
-#define CFG_FAULT_ECHO_LINK_DOWN
-#define CFG_FEC0_PINMUX		0
-#define CFG_FEC0_MIIBASE	CFG_FEC0_IOBASE
-#define CFG_FEC1_PINMUX		0
-#define CFG_FEC1_MIIBASE	CFG_FEC1_IOBASE
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX		0
+#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
 #define MCFFEC_TOUT_LOOP	50000
 #define CONFIG_HAS_ETH1
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
 #define FECDUPLEX		FULL
 #define FECSPEED		_100BASET
 #else
-#ifndef CFG_FAULT_ECHO_LINK_DOWN
-#define CFG_FAULT_ECHO_LINK_DOWN
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #endif
 #endif
 #endif
@@ -114,40 +114,40 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
 #undef CONFIG_SOFT_I2C
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x00000300
-#define CFG_IMMR		CFG_MBAR
-#define CFG_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
-#define CFG_I2C_PINMUX_CLR	(0xFFF0)
-#define CFG_I2C_PINMUX_SET	(0x000F)
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
+#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
+#define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)
 
 #ifdef CONFIG_MCFFEC
 #define CONFIG_ETHADDR		00:06:3b:01:41:55
 #define CONFIG_ETH1ADDR		00:0e:0c:bc:e5:60
 #endif
 
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
 
 #if (CONFIG_CMD_KGDB)
-#	define CFG_CBSIZE	1024
+#	define CONFIG_SYS_CBSIZE	1024
 #else
-#	define CFG_CBSIZE	256
+#	define CONFIG_SYS_CBSIZE	256
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE		CFG_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CFG_LOAD_ADDR		0x800000
+#define CONFIG_SYS_LOAD_ADDR		0x800000
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTCOMMAND	"bootm ffe40000"
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
-#define CFG_CLK			150000000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			150000000
 
 /*
  * Low Level Configuration Settings
@@ -155,73 +155,73 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x40000000
+#define CONFIG_SYS_MBAR		0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE	1000	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	1000	/* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
 
 #ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
+#define CONFIG_SYS_MONITOR_BASE	0x20000
 #else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial mmap for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial mmap for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT	1000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_SIZE		0x200000
+#define CONFIG_SYS_FLASH_SIZE		0x200000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CFG_AR0_PRELIM		(CFG_FLASH_BASE >> 16)
-#define CFG_CR0_PRELIM		0x1980
-#define CFG_MR0_PRELIM		0x001F0001
+#define CONFIG_SYS_AR0_PRELIM		(CONFIG_SYS_FLASH_BASE >> 16)
+#define CONFIG_SYS_CR0_PRELIM		0x1980
+#define CONFIG_SYS_MR0_PRELIM		0x001F0001
 
-#define CFG_AR1_PRELIM		0x3000
-#define CFG_CR1_PRELIM		0x1900
-#define CFG_MR1_PRELIM		0x00070001
+#define CONFIG_SYS_AR1_PRELIM		0x3000
+#define CONFIG_SYS_CR1_PRELIM		0x1900
+#define CONFIG_SYS_MR1_PRELIM		0x00070001
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CFG_FECI2C		0x0FA0
+#define CONFIG_SYS_FECI2C		0x0FA0
 
 #endif	/* _M5275EVB_H */