Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

1 files changed, 61 insertions, 61 deletions

diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 6bf2d99..e3830e5 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -40,9 +40,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef  CONFIG_WATCHDOG
 
@@ -62,38 +62,38 @@
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_NET
 
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
 #define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
 #define CONFIG_LOOPW		1	/* enable loopw command	*/
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 /*
  * Clock configuration: enable only one of the following options
  */
 
-#undef  CFG_PLL_BYPASS				/* bypass PLL for test purpose */
-#define CFG_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
-#define	CFG_CLK			132025600	/* MCF5249 can run at 140MHz   */
+#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
+#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
 
 /*
  * Low Level Configuration Settings
@@ -101,94 +101,94 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define	CFG_MBAR2		0x80000000
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CONFIG_SYS_MBAR2		0x80000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
-#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		(CFG_CSAR0 << 16)
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 
 #if 0 /* test-only */
 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
 #endif
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_CHECKSUM
-#	define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CFG_CSAR0		0xffe0
-#define	CFG_CSCR0		0x1980		/* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CFG_CSMR0		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CFG_CSAR1		0xe000
-#define	CFG_CSCR1		0x0d80		/* WS=0011, AA=1, PS=10         */
-#define	CFG_CSMR1		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define	CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
-#define	CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
-#define	CFG_GPIO_EN		0x00000008	/* Set gpio output enable       */
-#define	CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
-#define	CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
-#define	CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
-#define CFG_GPIO1_LED		0x00400000	/* user led                     */
+#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
+#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */
 
 #endif	/* M5249 */