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| author | TsiChung Liew <tsicliew@gmail.com> | 2010-03-11 22:12:53 -0600 |
|---|---|---|
| committer | TsiChung Liew <tsicliew@gmail.com> | 2010-03-24 11:09:37 -0500 |
| commit | dd9f054ede433de73b137987fb3dc066e8d24ebb (patch) | |
| tree | c4bafde866a253612976f0f3f8805093360c5c44 /include/configs/M5208EVBE.h | |
| parent | f628e2f72daee810aa568619b6629da68ad042d6 (diff) | |
| download | u-boot-imx-dd9f054ede433de73b137987fb3dc066e8d24ebb.zip u-boot-imx-dd9f054ede433de73b137987fb3dc066e8d24ebb.tar.gz u-boot-imx-dd9f054ede433de73b137987fb3dc066e8d24ebb.tar.bz2 | |
ColdFire: Cache update for all platforms
The CF will call cache functions in lib_m68/cache.c and the
cache settings are defined in platform configuration file.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Diffstat (limited to 'include/configs/M5208EVBE.h')
| -rw-r--r-- | include/configs/M5208EVBE.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 3cc259f..e6632ac 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -207,6 +207,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chipselect bank definitions */ /* * CS0 - NOR Flash |