* Patch by Klaus Heydeck, 13 Mar 2003:

  Add support for KUP4X Board

1 files changed, 69 insertions, 81 deletions

diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index 962a468..d6aa8e1 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
  *
@@ -13,7 +13,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -38,7 +38,7 @@
 #define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
 #define CONFIG_KUP4K		1	/* ...on a KUP4K module */
 
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		115200	/* console baudrate		*/
@@ -48,7 +48,7 @@
 #define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
 #endif
 
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
@@ -56,35 +56,38 @@
 #undef	CONFIG_BOOTARGS
 
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					  \
-"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
- diskboot 200000 0:1; bootm 200000\0"                                     \
-"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
- diskboot 200000 2:1; bootm 200000\0"                                     \
-"nfs_boot=dhcp; run nfsargs addip; bootm 200000\0"                        \
-"panic_boot=echo No Bootdevice !!! reset\0"                               \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath)\0" \
-"ramargs=setenv bootargs root=/dev/ram rw\0"			          \
-"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsip):$(gatewayip)\
-:$(netmask):$(hostname):$(netdev):off panic=1\0"                          \
-"netdev=eth0\0"                                                           \
-"load=tftp 200000 bootloader.bitmap;tftp 100000 u-boot.bin\0"             \
-"update=protect off 1:0-8;era 1:0-8;cp.b 100000 40000000 $(filesize);\
-cp.b 200000 40040000 14000\0"                                                   \
-"nfsip=192.168.2.19\0"
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
+ "run addhw; diskboot 200000 0:1; bootm 200000\0"				\
+"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
+ "run addhw; diskboot 200000 2:1; bootm 200000\0"				\
+"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0"			\
+"panic_boot=echo No Bootdevice !!! reset\0"					\
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"	\
+"ramargs=setenv bootargs root=/dev/ram rw\0"					\
+"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)"	\
+ ":$(netmask):$(hostname):$(netdev):off\0"					\
+"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0"		\
+"netdev=eth0\0"									\
+"contrast=55\0"									\
+"silent=1\0"									\
+"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
+"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);"		\
+ "cp.b 200000 40040000 14000\0"
 
 #define CONFIG_BOOTCOMMAND  \
     "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
 
 
-#define CONFIG_MISC_INIT_R  1
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_MISC_INIT_F	1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
 
 #undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
 
@@ -93,10 +96,14 @@ cp.b 200000 40040000 14000\0"
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
-#define CONFIG_KUP4K_LOGO               0x40040000  /* Address of logo bitmap */
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED	40000
+#define CFG_I2C_SLAVE	0x7F
+
+#define CONFIG_ETHADDR			00:0B:64:00:00:00 /* our OUI from IEEE */
+#define CONFIG_KUP4K_LOGO		0x40040000  /* Address of logo bitmap */
 
 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -104,6 +111,7 @@ cp.b 200000 40040000 14000\0"
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_IDE	| \
+				CFG_CMD_I2C	| \
 				CFG_CMD_DATE	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -112,25 +120,25 @@ cp.b 200000 40040000 14000\0"
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_START	0x000400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x002C00000	/* 4 ... 44 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x200000	/* default load address	*/
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
 
 #define CFG_CONSOLE_INFO_QUIET 1
 
@@ -148,42 +156,42 @@ cp.b 200000 40040000 14000\0"
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE       0x8000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x30000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000
 
 /* Address and size of Redundant Environment Sector	*/
 #if 0
@@ -195,7 +203,7 @@ cp.b 200000 40040000 14000\0"
  */
 #if 0
 #define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
 #define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 #endif
 /*-----------------------------------------------------------------------
@@ -275,7 +283,7 @@ cp.b 200000 40040000 14000\0"
  */
 
 /* KUP4K use both slots, SLOT_A as "primary". */
-#define	CONFIG_PCMCIA_SLOT_A 1
+#define CONFIG_PCMCIA_SLOT_A 1
 
 #define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
@@ -293,10 +301,10 @@ cp.b 200000 40040000 14000\0"
  *-----------------------------------------------------------------------
  */
 
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
 
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#define CONFIG_IDE_LED			1   /* LED   for ide supported	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#define CONFIG_IDE_LED		1	/* LED	 for ide supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
 #define CFG_IDE_MAXBUS		2
@@ -323,7 +331,7 @@ cp.b 200000 40040000 14000\0"
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CFG_DER 0
 
 /*
  * Init Memory Controller:
@@ -350,29 +358,9 @@ cp.b 200000 40040000 14000\0"
 #define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE2_PRELIM	0x20000000	/* SDRAM bank #1	*/
-#define SDRAM_BASE3_PRELIM	0x30000000	/* SDRAM bank #2	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 648 MB per bank	*/
-
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
 #define CFG_OR_TIMING_SDRAM	0x00000A00
 
-#if 0
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define CFG_OR3_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#endif
-
 
 /*
  * Memory Periodic Timer Prescaler
@@ -388,11 +376,11 @@ cp.b 200000 40040000 14000\0"
  *	gclk	  CPU clock (not bus clock!)
  *	Trefresh  Refresh cycle * 4 (four word bursts used)
  *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
+ * 4096	 Rows from SDRAM example configuration
+ * 1000	 factor s -> ms
+ *   32	 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4	 Number of refresh cycles per period
+ *   64	 Refresh cycle in ms per number of rows
  * --------------------------------------------
  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  *
@@ -428,7 +416,7 @@ cp.b 200000 40040000 14000\0"
  *
  * Boot Flags
  */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
 
@@ -437,6 +425,6 @@ cp.b 200000 40040000 14000\0"
 #define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
 #endif
 #define CONFIG_AUTOBOOT_STOP_STR	"." /* easy to stop for now */
-
+#define CONFIG_SILENT_CONSOLE	1
 
 #endif	/* __CONFIG_H */