rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 67 insertions, 67 deletions

diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index eeb3924..403081d 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -43,7 +43,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
 #define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
 #define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
-#undef	CFG_DRAM_TEST			     /* Disable-takes long time!*/
+#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
 #define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
 
 #define CONFIG_VERY_BIG_RAM 1
@@ -55,38 +55,38 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
-#define CFG_MONITOR_BASE       0xfff80000    /* start of monitor	*/
-#define CFG_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
-#define CFG_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
-
-#define CFG_NVRAM_BASE_ADDR   (CFG_PERIPHERAL_BASE + 0x08000000)
-#define CFG_KAREF_FPGA_BASE   (CFG_PERIPHERAL_BASE + 0x08200000)
-#define CFG_OFEM_FPGA_BASE    (CFG_PERIPHERAL_BASE + 0x08400000)
-#define CFG_BME32_BASE	      (CFG_PERIPHERAL_BASE + 0x08500000)
-#define CFG_GPIO_BASE	      (CFG_PERIPHERAL_BASE + 0x00000700)
+#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
+#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
+#define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
+#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
+#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
 
 /* Here for completeness */
-#define CFG_OFEMAC_BASE	      (CFG_PERIPHERAL_BASE + 0x08600000)
+#define CONFIG_SYS_OFEMAC_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM    1
-#define CFG_OCM_DATA_ADDR     CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR     CFG_ISRAM_BASE /* Initial RAM address	*/
-#define CFG_INIT_RAM_END      0x2000	     /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
+#define CONFIG_SYS_TEMP_STACK_OCM    1
+#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END      0x2000	     /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
 
-#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR    (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET    CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
-#define CFG_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
+#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -95,7 +95,7 @@
 #define CONFIG_SERIAL_MULTI   1
 #define CONFIG_BAUDRATE	      9600
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
@@ -105,21 +105,21 @@
  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  * address for the RTC registers is:
  *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
 #define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS   1		     /* number of banks		*/
-#define CFG_MAX_FLASH_SECT    8		     /* sectors per device	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
-#define CFG_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -132,9 +132,9 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
 #undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
-#define CFG_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
-#define CFG_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
-#define CFG_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
+#define CONFIG_SYS_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
+#define CONFIG_SYS_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
 #define CONFIG_I2C_BUS1	      1		     /* Include i2c bus 1 supp	*/
 
 
@@ -147,12 +147,12 @@
 #define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
 
 #define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
-#define CONFIG_ENV_ADDR	      (CFG_NVRAM_BASE_ADDR)
+#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
 
 #define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */
 
 #define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
-#define CFG_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
 
 /*-----------------------------------------------------------------------
  * Networking
@@ -175,7 +175,7 @@
 #define CONFIG_NETMASK	      255.255.0.0
 #define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
 #define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
-#define CFG_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
+#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
 
 
 /*
@@ -212,33 +212,33 @@
 
 /* Include auto complete with tabs */
 #define CONFIG_AUTO_COMPLETE 1
-#define CFG_ALT_MEMTEST	     1	     /* use real memory test	 */
+#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
 
-#define CFG_LONGHELP			     /* undef to save memory	*/
-#define CFG_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
-#define CFG_PROMPT_HUSH_PS2    "> "
+#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2    "> "
 
 
 /*-----------------------------------------------------------------------
  * Console Buffer
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	      1024	     /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	      256	     /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 					     /* Print Buffer Size	*/
-#define CFG_MAXARGS	      16	     /* max number of cmd args	*/
-#define CFG_BARGSIZE	      CFG_CBSIZE     /* Boot Arg Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
+#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
 
 /*-----------------------------------------------------------------------
  * Memory Test
  *----------------------------------------------------------------------*/
-#define CFG_MEMTEST_START     0x0400000	     /* memtest works on	*/
-#define CFG_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
 
 /*-----------------------------------------------------------------------
  * Compact Flash (in true IDE mode)
@@ -247,16 +247,16 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 
 #define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0000000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
-#define CFG_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
 
-#define CFG_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
+#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
 					    to get to the correct offset */
 #define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
 
@@ -267,20 +267,20 @@
 #define CONFIG_PCI			     /* include pci support	*/
 #define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
 #define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
-#define CFG_PCI_TARGBASE      (CFG_PCI_MEMBASE)
+#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		     /* let board init pci target*/
+#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
@@ -299,10 +299,10 @@
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
-#define CFG_LOAD_ADDR	      0x8000000	     /* default load address	*/
-#define CFG_EXTBDINFO	      1		     /* use extended board_info */
+#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
 
-#define CFG_HZ		      100	     /* decr freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		      100	     /* decr freq: 1 ms ticks	*/
 
 
 #endif	/* __CONFIG_H */