rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 95 insertions, 95 deletions

diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 54477ee..125cb4b 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -66,7 +66,7 @@
 				"nfsaddrs=10.0.0.99:10.0.0.2"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -95,34 +95,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
 
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
-#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
-#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
+#define CONFIG_SYS_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
+#define CONFIG_SYS_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
 
-#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
-#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
+#define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -132,53 +132,53 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
 #if defined (CONFIG_IVMS8_16M)
-# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
 #elif defined (CONFIG_IVMS8_32M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
 #elif defined (CONFIG_IVMS8_64M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
 #endif
 
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
 #ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
@@ -186,9 +186,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -199,17 +199,17 @@
  */
 #if defined(CONFIG_WATCHDOG)
 # if defined (CONFIG_IVMS8_16M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #  elif defined (CONFIG_IVMS8_32M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 #  elif defined (CONFIG_IVMS8_64M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 #  endif
 #else
-# define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+# define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -219,21 +219,21 @@
  */
 /* EARB, DBGC and DBPC are initialised by the HCW */
 /* => 0x000000C0 */
-#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -242,7 +242,7 @@
  * interrupt status bit, set PLL multiplication factor !
  */
 /* 0x00B0C0C0 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		(	(11 << PLPRCR_MF_SHIFT) |			\
 			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
@@ -257,7 +257,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* 0x01800014 */
-#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
+#define CONFIG_SYS_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
@@ -270,7 +270,7 @@
  *-----------------------------------------------------------------------
  */
 /* 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
@@ -278,34 +278,34 @@
  *-----------------------------------------------------------------------
  */
 /* TIMEP=2 */
-#define CFG_RCCR 0x0200
+#define CONFIG_SYS_RCCR 0x0200
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  *
  * Interrupt Levels
  *-----------------------------------------------------------------------
  */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -314,23 +314,23 @@
 #define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
-#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
 
-#define CFG_ATA_BASE_ADDR	0xFE100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -345,17 +345,17 @@
  * but not too much to meddle with FLASH accesses
  */
 /* EPROMs are 512kb */
-#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 /* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
@@ -366,8 +366,8 @@
 #define ELIC_SACCO_OR_AM	0xFFFF8000
 #define ELIC_SACCO_TIMING	0x00000F26
 
-#define CFG_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
-#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
+#define CONFIG_SYS_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
@@ -378,8 +378,8 @@
 #define ELIC_EPIC_OR_AM		0xFFFF8000
 #define ELIC_EPIC_TIMING	0x00000F26
 
-#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
-#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
+#define CONFIG_SYS_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR3/OR3: SDRAM
@@ -392,8 +392,8 @@
 
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
 
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 
 /*
  * BR4/OR4: not used
@@ -408,28 +408,28 @@
 #define SHARC_OR_AM		0xFFC00000
 #define SHARC_TIMING		0x00000700
 
-#define CFG_OR5	(SHARC_OR_AM | SHARC_TIMING )
-#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR5	(SHARC_OR_AM | SHARC_TIMING )
+#define CONFIG_SYS_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MBMR_PTB	204
+#define CONFIG_SYS_MBMR_PTB	204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
 #if defined (CONFIG_IVMS8_16M)
- #define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+ #define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 #elif defined (CONFIG_IVMS8_32M)
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 #elif defined (CONFIG_IVMS8_64M)
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
 #endif
 
 
@@ -439,17 +439,17 @@
 
 #if defined (CONFIG_IVMS8_16M)
  /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_32M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_64M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)