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| author | Stefan Roese <sr@denx.de> | 2006-02-07 16:51:04 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2006-02-07 16:51:04 +0100 |
| commit | 48a05a5188e03861da2378c95ba7963d810736aa (patch) | |
| tree | 172110c356d3665a2c6315855270b88156ac9e34 /include/configs/HH405.h | |
| parent | 57cac1fa547fa590fe4b7992619b9f26417014c3 (diff) | |
| download | u-boot-imx-48a05a5188e03861da2378c95ba7963d810736aa.zip u-boot-imx-48a05a5188e03861da2378c95ba7963d810736aa.tar.gz u-boot-imx-48a05a5188e03861da2378c95ba7963d810736aa.tar.bz2 | |
Various changes to esd HH405 board specific files
Patch by Matthias Fuchs, 07 Feb 2006
Diffstat (limited to 'include/configs/HH405.h')
| -rw-r--r-- | include/configs/HH405.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 131c215..4f62b8a 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -5,6 +5,9 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2006 + * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -61,9 +64,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -79,6 +86,7 @@ #else #define CONFIG_VIDEO_SM501_16BPP #endif +#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_VGA_AS_SINGLE_DEVICE @@ -434,9 +442,12 @@ #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008 #define CFG_FPGA_CTRL_CF_RESET 0x0040 #define CFG_FPGA_CTRL_PS2_PWR 0x0080 -#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */ +#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */ #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200 #define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */ +#define CFG_FPGA_CTRL_OW_ENABLE 0x8000 + +#define CFG_FPGA_STATUS_CF_DETECT 0x8000 #define LCD_CLK_OFF 0x0000 /* Off */ #define LCD_CLK_02083 0x1000 /* 2.083 MHz */ |