Merge branch 'master' of /home/stefan/git/u-boot/u-boot

1 files changed, 42 insertions, 44 deletions

diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index c8b5a6d..037b115 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -39,9 +39,9 @@
  * Identify the board
  */
 #if !defined(CONFIG_SC)
-#define CONFIG_IDENT_STRING				" B2"
+#define CONFIG_IDENT_STRING		" B2"
 #else
-#define CONFIG_IDENT_STRING				" SC"
+#define CONFIG_IDENT_STRING		" SC"
 #endif
 
 /*
@@ -50,26 +50,26 @@
  * generated by the DS1337 - and the DS1337 clock can be turned off.
  */
 #if !defined(CONFIG_SC)
-#define	CONFIG_8xx_GCLK_FREQ			66600000
+#define	CONFIG_8xx_GCLK_FREQ		66600000
 #else
-#define	CONFIG_8xx_GCLK_FREQ			48000000
+#define	CONFIG_8xx_GCLK_FREQ		48000000
 #endif
 
 /*
  * The RS-232 console port is on SMC1
  */
 #define	CONFIG_8xx_CONS_SMC1
-#define CONFIG_BAUDRATE					38400
+#define CONFIG_BAUDRATE			38400
 
 /*
  * Set allowable console baud rates
  */
-#define CFG_BAUDRATE_TABLE				{ 9600,		\
-							 		 	  19200,	\
-							 		 	  38400,	\
-									 	  57600,	\
-									 	  115200,	\
-										}
+#define CFG_BAUDRATE_TABLE		{ 9600,		\
+					  19200,	\
+					  38400,	\
+					  57600,	\
+					  115200,	\
+					}
 
 /*
  * Print console information
@@ -148,7 +148,7 @@
 #define CFG_DISCOVER_PHY
 #define CONFIG_MII
 #define CONFIG_MII_INIT			1
-#define CONFIG_PHY_ADDR         		0
+#define CONFIG_PHY_ADDR			0
 
 /*
  * Set default IP stuff just to get bootstrap entries into the
@@ -172,7 +172,7 @@
  * Enable I2C and select the hardware/software driver
  */
 #define CONFIG_HARD_I2C		1				/* CPM based I2C			*/
-#undef	CONFIG_SOFT_I2C        				/* Bit-banged I2C			*/
+#undef	CONFIG_SOFT_I2C						/* Bit-banged I2C			*/
 
 #ifdef CONFIG_HARD_I2C
 #define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
@@ -181,7 +181,7 @@
 
 #ifdef CONFIG_SOFT_I2C
 #define PB_SCL				0x00000020		/* PB 26					*/
-#define PB_SDA				0x00000010		/* PB 27 					*/
+#define PB_SDA				0x00000010		/* PB 27					*/
 #define I2C_INIT			(immr->im_cpm.cp_pbdir |=  PB_SCL)
 #define I2C_ACTIVE			(immr->im_cpm.cp_pbdir |=  PB_SDA)
 #define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
@@ -388,7 +388,7 @@
  */
 #define CFG_INIT_RAM_ADDR		CFG_IMMR
 #define	CFG_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
-#define	CFG_INIT_DATA_SIZE		64  	/* # bytes reserved for initial data*/
+#define	CFG_INIT_DATA_SIZE		64	/* # bytes reserved for initial data*/
 #define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 #define	CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
 
@@ -480,18 +480,18 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR	( SYPCR_SWTC	| \
-					  SYPCR_BMT 	| \
-					  SYPCR_BME 	| \
-					  SYPCR_SWF 	| \
-					  SYPCR_SWE 	| \
+					  SYPCR_BMT	| \
+					  SYPCR_BME	| \
+					  SYPCR_SWF	| \
+					  SYPCR_SWE	| \
 					  SYPCR_SWRI	| \
 					  SYPCR_SWP		  \
 					)
 #else
 #define CFG_SYPCR	( SYPCR_SWTC	| \
-					  SYPCR_BMT 	| \
-					  SYPCR_BME 	| \
-					  SYPCR_SWF 	| \
+					  SYPCR_BMT	| \
+					  SYPCR_BME	| \
+					  SYPCR_SWF	| \
 					  SYPCR_SWP		  \
 					)
 #endif
@@ -557,18 +557,18 @@
 #define SCCR_MASK   SCCR_EBDF11
 
 #if !defined(CONFIG_SC)
-#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
-					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
-					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
-					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
+#define CFG_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
 					  SCCR_DFNL000		| \
 					  SCCR_DFNH000		  \
 					)
 #else
-#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
-					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
-					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
-					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
+#define CFG_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
 					  SCCR_DFNL000		| \
 					  SCCR_DFNH000		| \
 					  SCCR_RTDIV		| \
@@ -614,7 +614,7 @@
 #define CFG_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
 						  BR_MS_GPCM						| \
 						  BR_PS_8							| \
-						  BR_V 								  \
+						  BR_V								  \
 						)
 
 /*
@@ -626,9 +626,9 @@
 					)
 
 #define CFG_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
-					  BR_MS_UPMA 				| \
-					  BR_PS_32	 				| \
-					  BR_V 						  \
+					  BR_MS_UPMA				| \
+					  BR_PS_32					| \
+					  BR_V						  \
 					)
 
 /*
@@ -646,9 +646,9 @@
  * MAMR settings for SDRAM
  */
 #define CFG_MAMR_8COL	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)	| \
-						  MAMR_PTAE	    			| \
+						  MAMR_PTAE				| \
 						  MAMR_AMA_TYPE_1			| \
-						  MAMR_DSA_1_CYCL 			| \
+						  MAMR_DSA_1_CYCL			| \
 						  MAMR_G0CLA_A10			| \
 						  MAMR_RLFA_1X				| \
 						  MAMR_WLFA_1X				| \
@@ -660,7 +660,7 @@
  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
  * no burst.
  */
-#define CFG_OR2_PRELIM 	( (0xffff0000 & OR_AM_MSK)	| \
+#define CFG_OR2_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
 						  OR_CSNT_SAM				| \
 						  OR_ACS_DIV2				| \
 						  OR_BI						| \
@@ -685,20 +685,20 @@
  */
 #define CFG_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
 						  OR_SCY_15_CLK				| \
-						  OR_BI 					  \
+						  OR_BI					  \
 						)
 
 #define CFG_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
 						  BR_PS_32					| \
 						  BR_MS_GPCM				| \
-						  BR_V		  				  \
+						  BR_V						  \
 						)
 /*
  * CS4* configuration for FPGA SelectMap configuration interface.
  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
  * of GCLK1_50
  */
-#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)  	| \
+#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
 						  OR_G5LS						| \
 						  OR_BI							  \
 						)
@@ -706,7 +706,7 @@
 #define CFG_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
 						  BR_PS_8						| \
 						  BR_MS_UPMB					| \
-						  BR_V			  				  \
+						  BR_V							  \
 						)
 
 /*
@@ -728,7 +728,7 @@
 #define CFG_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
 						  BR_PS_16					| \
 						  BR_MS_GPCM				| \
-						  BR_V			  			  \
+						  BR_V						  \
 						)
 
 /*
@@ -760,5 +760,3 @@
 #endif
 
 #endif	/* __CONFIG_GEN860T_H */
-
-/* vim: set ts=4 tw=78 ai shiftwidth=4: */