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| author | Wolfgang Denk <wd@denx.de> | 2009-07-19 00:38:23 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-07-19 00:38:23 +0200 |
| commit | a694610d3361465d4c8d27dde72ab8b63d31115e (patch) | |
| tree | 063d03bcf75538fe45f940eda5b1e6f1859a96fb /include/configs/G2000.h | |
| parent | 5669ed4557edf2714203aa8625c9fcd5a753b338 (diff) | |
| parent | 2419169f5749d7af501b3b77a5336d1d535320de (diff) | |
| download | u-boot-imx-a694610d3361465d4c8d27dde72ab8b63d31115e.zip u-boot-imx-a694610d3361465d4c8d27dde72ab8b63d31115e.tar.gz u-boot-imx-a694610d3361465d4c8d27dde72ab8b63d31115e.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
Diffstat (limited to 'include/configs/G2000.h')
| -rw-r--r-- | include/configs/G2000.h | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/include/configs/G2000.h b/include/configs/G2000.h index bf9fd82..6819c3e 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -196,32 +196,12 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CONFIG_SYS_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) #endif /*----------------------------------------------------------------------- |