Merge git://git.denx.de/u-boot into x1

Conflicts:

	drivers/usb/usb_ohci.c

1 files changed, 111 insertions, 110 deletions

diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index 9f8c423..508a0ca 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -45,53 +45,52 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN		(8 << 20)	/* Reserve 8 MB for malloc()  */
-
-#define CFG_BOOT_BASE_ADDR	0xf0000000
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_NAND0_ADDR		0xd0000000      /* NAND Flash		*/
-#define CFG_NAND1_ADDR		0xd0100000      /* NAND Flash		*/
-#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
-#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
-#define CFG_PCI_IOBASE          0xe8000000
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(8 << 20)	/* Reserve 8 MB for malloc()  */
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_NAND0_ADDR		0xd0000000      /* NAND Flash		*/
+#define CONFIG_SYS_NAND1_ADDR		0xd0100000      /* NAND Flash		*/
+#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_IOBASE          0xe8000000
 
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 
-#define CFG_USB2D0_BASE		0xe0000100
-#define CFG_USB_DEVICE		0xe0000000
-#define CFG_USB_HOST		0xe0000400
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
 
 /*
  * Initial RAM & stack pointer
  */
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_OCM	1		/* OCM as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Serial Port
  */
-/* TODO: external clock oscillator will be removed */
-#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI     1
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE						\
+#define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*
@@ -105,10 +104,10 @@
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
-#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
-#define CFG_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
-#define CFG_CONSOLE_IS_IN_ENV
-#define CFG_ISA_IO CFG_PCI_IOBASE
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
+#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
 
 /*
  * Environment
@@ -118,27 +117,27 @@
 /*
  * FLASH related
  */
-#define CFG_FLASH_CFI			/* The flash is CFI compatible */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible */
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver       */
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection      */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
 
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector        */
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
 
 /* Address and size of Redundant Environment Sector	*/
@@ -155,9 +154,9 @@
 /*
  * DDR SDRAM
  */
-#define CFG_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
+#define CONFIG_SYS_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization        */
-#define CFG_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
+#define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
 					/* 440EPx errata CHIP 11        */
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup     */
 #define CONFIG_DDR_ECC			/* Use ECC when available       */
@@ -169,27 +168,26 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged	        */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address  */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_I2C_CMD_TREE     1
 #define CONFIG_I2C_MULTI_BUS    1
 
-#define CFG_SPD_BUS_NUM         0
+#define CONFIG_SYS_SPD_BUS_NUM         0
 #define IIC1_MCP3021_ADDR	0x4d
 #define IIC1_USB2507_ADDR	0x2c
 #ifdef CONFIG_I2C_MULTI_BUS
-#define CFG_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
+#define CONFIG_SYS_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
 #endif
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	0x54
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
 
-#define CFG_EEPROM_WREN         1
-#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
+#define CONFIG_SYS_EEPROM_WREN         1
+#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
@@ -209,13 +207,13 @@
  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
  */
 #define CONFIG_DTT_ADM1021
-#define CFG_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 
 /*
  * RTC stuff
  */
 #define CONFIG_RTC_DS1338
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 #undef	CONFIG_BOOTARGS
 
@@ -249,7 +247,7 @@
 #define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #ifndef __ASSEMBLY__
 int du440_phy_addr(int devnum);
@@ -263,7 +261,7 @@ int du440_phy_addr(int devnum);
 #undef CONFIG_PHY_GIGE			/* no GbE detection		*/
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	128
+#define CONFIG_SYS_RX_ETH_BUFFER	128
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
@@ -274,12 +272,12 @@ int du440_phy_addr(int devnum);
  */
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
-#define CFG_OHCI_BE_CONTROLLER
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
 
-#define CFG_USB_OHCI_CPU_INIT	1
-#define CFG_USB_OHCI_REGS_BASE	CFG_USB_HOST
-#define CFG_USB_OHCI_SLOT_NAME	"du440"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"du440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
@@ -319,25 +317,25 @@ int du440_phy_addr(int devnum);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
 /* Print Buffer Size */
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x3f000000 /* 4 ... < 1GB DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x3f000000 /* 4 ... < 1GB DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -357,65 +355,65 @@ int du440_phy_addr(int devnum);
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CFG_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)     /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)     /* Initial Memory map for Linux */
 
 /*
  * External Bus Controller (EBC) Setup
  */
-#define CFG_FLASH		CFG_FLASH_BASE
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
 
-#define CFG_CPLD_BASE		0xC0000000
-#define CFG_CPLD_RANGE	        0x00000010
-#define CFG_DUMEM_BASE		0xC0100000
-#define CFG_DUMEM_RANGE		0x00100000
-#define CFG_DUIO_BASE		0xC0200000
-#define CFG_DUIO_RANGE	        0x00010000
+#define CONFIG_SYS_CPLD_BASE		0xC0000000
+#define CONFIG_SYS_CPLD_RANGE	        0x00000010
+#define CONFIG_SYS_DUMEM_BASE		0xC0100000
+#define CONFIG_SYS_DUMEM_RANGE		0x00100000
+#define CONFIG_SYS_DUIO_BASE		0xC0200000
+#define CONFIG_SYS_DUIO_RANGE	        0x00010000
 
-#define CFG_NAND0_CS		2		/* NAND chip connected to CSx */
-#define CFG_NAND1_CS		3		/* NAND chip connected to CSx */
+#define CONFIG_SYS_NAND0_CS		2		/* NAND chip connected to CSx */
+#define CONFIG_SYS_NAND1_CS		3		/* NAND chip connected to CSx */
 /* Memory Bank 0 (NOR-FLASH) initialization */
-#define CFG_EBC_PB0AP		0x04017200
-#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)
+#define CONFIG_SYS_EBC_PB0AP		0x04017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 
 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
-#define CFG_EBC_PB1AP		0x018003c0
-#define CFG_EBC_PB1CR		(CFG_CPLD_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB1AP		0x018003c0
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
 
 /* Memory Bank 2 (NAND-FLASH) initialization */
-#define CFG_EBC_PB2AP		0x018003c0
-#define CFG_EBC_PB2CR		(CFG_NAND0_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB2AP		0x018003c0
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND0_ADDR | 0x1c000)
 
 /* Memory Bank 3 (NAND-FLASH) initialization */
-#define CFG_EBC_PB3AP		0x018003c0
-#define CFG_EBC_PB3CR		(CFG_NAND1_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND1_ADDR | 0x1c000)
 
 /* Memory Bank 4 (DUMEM, 1MB) initialization */
-#define CFG_EBC_PB4AP		0x018053c0
-#define CFG_EBC_PB4CR		(CFG_DUMEM_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB4AP		0x018053c0
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_DUMEM_BASE | 0x18000)
 
 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
-#define CFG_EBC_PB5AP		0x018053c0
-#define CFG_EBC_PB5CR		(CFG_DUIO_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB5AP		0x018053c0
+#define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_DUIO_BASE | 0x18000)
 
 /*
  * NAND FLASH
  */
-#define CFG_MAX_NAND_DEVICE	2
-#define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
-#define CFG_NAND_BASE_LIST	{CFG_NAND0_ADDR + CFG_NAND0_CS, \
-				 CFG_NAND1_ADDR + CFG_NAND1_CS}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define NAND_MAX_CHIPS		CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
+				 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
 
 /*
  * Internal Definitions
@@ -432,4 +430,7 @@ int du440_phy_addr(int devnum);
 
 #define CONFIG_AUTOSCRIPT	1
 
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
 #endif	/* __CONFIG_H */