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| author | Stefan Roese <sr@denx.de> | 2010-09-12 06:21:37 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-09-23 09:02:05 +0200 |
| commit | afabb498b749b48ca3ee7e833fe1501e2d6993cb (patch) | |
| tree | a5e131d0d7f62e41bd9bc1c767452b43b75bf82e /include/configs/DP405.h | |
| parent | 5e7abce99163a00b8d267cc8045f06b498728288 (diff) | |
| download | u-boot-imx-afabb498b749b48ca3ee7e833fe1501e2d6993cb.zip u-boot-imx-afabb498b749b48ca3ee7e833fe1501e2d6993cb.tar.gz u-boot-imx-afabb498b749b48ca3ee7e833fe1501e2d6993cb.tar.bz2 | |
ppc4xx: Big header cleanup part 2, mostly PPC405 related
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.
As a part from this cleanup, the GPIO definitions for PPC405EP are
corrected. The high and low parts of the registers (for example
CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in
the wrong order. This patch now fixes this issue by switching these
xxxH and xxxL values. This brings the GPIO 405EP port in sync with all
other PPC4xx ports.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/DP405.h')
| -rw-r--r-- | include/configs/DP405.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 4423f2a..0ee456b 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -243,12 +243,12 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000540 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ /* |