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| author | Stefan Roese <sr@denx.de> | 2007-08-15 14:51:27 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-15 14:51:27 +0200 |
| commit | d61ea14885631e58a25feaa81ee82eb464c62d6a (patch) | |
| tree | 27927975039d0a15e6c6d4dfe8f765a76a12820a /include/configs/DP405.h | |
| parent | 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 (diff) | |
| parent | 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 (diff) | |
| download | u-boot-imx-d61ea14885631e58a25feaa81ee82eb464c62d6a.zip u-boot-imx-d61ea14885631e58a25feaa81ee82eb464c62d6a.tar.gz u-boot-imx-d61ea14885631e58a25feaa81ee82eb464c62d6a.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/configs/DP405.h')
| -rw-r--r-- | include/configs/DP405.h | 38 |
1 files changed, 25 insertions, 13 deletions
diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 2ae794d..2eadbea 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -55,17 +55,29 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -87,7 +99,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -235,7 +247,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif |