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| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /include/configs/DK1S10_safe_32.h | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
| download | u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.zip u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.gz u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.bz2 | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'include/configs/DK1S10_safe_32.h')
0 files changed, 0 insertions, 0 deletions