Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 135 insertions, 135 deletions

diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index e087624..489378a 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -87,10 +87,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -100,10 +100,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -129,8 +129,8 @@
  */
 #define CONFIG_SOFT_I2C			/* Software I2C support enabled */
 
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -145,7 +145,7 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -153,17 +153,17 @@
  * Disk-On-Chip configuration
  */
 
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configuration options
  */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 /*
  * BOOTP options
@@ -196,27 +196,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
 
 #define CONFIG_LOOPW
 
@@ -225,135 +225,135 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Flash configuration
  */
 
-#define CFG_BOOTROM_BASE	0xFF800000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Other areas to be mapped
  */
 
 /* CS3: Dual ported SRAM */
-#define CFG_DPSRAM_BASE		0x40000000
-#define CFG_DPSRAM_SIZE		0x00100000
+#define CONFIG_SYS_DPSRAM_BASE		0x40000000
+#define CONFIG_SYS_DPSRAM_SIZE		0x00100000
 
 /* CS4: DiskOnChip */
-#define CFG_DOC_BASE		0xF4000000
-#define CFG_DOC_SIZE		0x00100000
+#define CONFIG_SYS_DOC_BASE		0xF4000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
 
 /* CS5: FDC37C78 controller */
-#define CFG_FDC37C78_BASE	0xF1000000
-#define CFG_FDC37C78_SIZE	0x00100000
+#define CONFIG_SYS_FDC37C78_BASE	0xF1000000
+#define CONFIG_SYS_FDC37C78_SIZE	0x00100000
 
 /* CS6: Board configuration registers */
-#define CFG_BCRS_BASE		0xF2000000
-#define CFG_BCRS_SIZE		0x00010000
+#define CONFIG_SYS_BCRS_BASE		0xF2000000
+#define CONFIG_SYS_BCRS_SIZE		0x00010000
 
 /* CS7: VME Extended Access Range */
-#define CFG_VMEEAR_BASE		0x60000000
-#define CFG_VMEEAR_SIZE		0x01000000
+#define CONFIG_SYS_VMEEAR_BASE		0x60000000
+#define CONFIG_SYS_VMEEAR_SIZE		0x01000000
 
 /* CS8: VME Standard Access Range */
-#define CFG_VMESAR_BASE		0xFE000000
-#define CFG_VMESAR_SIZE		0x01000000
+#define CONFIG_SYS_VMESAR_BASE		0xFE000000
+#define CONFIG_SYS_VMESAR_SIZE		0x01000000
 
 /* CS9: VME Short I/O Access Range */
-#define CFG_VMESIOAR_BASE	0xFD000000
-#define CFG_VMESIOAR_SIZE	0x01000000
+#define CONFIG_SYS_VMESIOAR_BASE	0xFD000000
+#define CONFIG_SYS_VMESIOAR_SIZE	0x01000000
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 				 HRCW_BPS01 | HRCW_CS10PC01)
 #else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
 #endif
 
 #ifdef	CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
 #endif
 
 #if 0
 /* environment is in Flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #ifdef CONFIG_BOOT_ROM
-# define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x70000)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x70000)
 # define CONFIG_ENV_SIZE		0x10000
 # define CONFIG_ENV_SECT_SIZE	0x10000
 #endif
 #else
 /* environment is in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 #define CONFIG_ENV_OFFSET		512
 #define CONFIG_ENV_SIZE		(2048 - 512)
 #endif
@@ -370,9 +370,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -385,30 +385,30 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
 			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID0_FINAL	(HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register					 5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR		RMR_CSRE
+#define CONFIG_SYS_RMR		RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
 #define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 
 /*-----------------------------------------------------------------------
@@ -418,10 +418,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -431,7 +431,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -439,22 +439,22 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR	SCCR_DFBRG01
+#define CONFIG_SYS_SCCR	SCCR_DFBRG01
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
-#define CFG_MIN_AM_MASK 0xC0000000
+#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 
 /*
  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
@@ -465,13 +465,13 @@
  * MPTPR - Memory Refresh Timer Prescaler Register		10-18
  *-----------------------------------------------------------------------
  */
-#define CFG_MPTPR	0x2000
+#define CONFIG_SYS_MPTPR	0x2000
 
 /*-----------------------------------------------------------------------
  * PSRT - Refresh Timer Register				10-16
  *-----------------------------------------------------------------------
  */
-#define CFG_PSRT	0x16
+#define CONFIG_SYS_PSRT	0x16
 
 /*-----------------------------------------------------------------------
  * PSRT - SDRAM Mode Register					10-10
@@ -480,12 +480,12 @@
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A9		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
 			 PSDMR_BSMA_A14_A16		|\
 			 PSDMR_SDA10_PBI0_A10		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -497,12 +497,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A7		|\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
 			 PSDMR_BSMA_A13_A15		|\
 			 PSDMR_SDA10_PBI0_A9		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -514,12 +514,12 @@
 
 	/* SDRAM initialization values for 10-column chips
 	 */
-#define CFG_OR2_10COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_10COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI1_A4		|\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_10COL	(PSDMR_PBI			|\
+#define CONFIG_SYS_PSDMR_10COL	(PSDMR_PBI			|\
 			 PSDMR_SDAM_A17_IS_A5		|\
 			 PSDMR_BSMA_A13_A15		|\
 			 PSDMR_SDA10_PBI1_A6		|\
@@ -541,17 +541,17 @@
  *
  */
 
-#define CFG_MRS_OFFS	0x00000000
+#define CONFIG_SYS_MRS_OFFS	0x00000000
 
 #ifdef CONFIG_BOOT_ROM
 /* Bank 0 - Boot ROM
  */
-#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -559,12 +559,12 @@
 
 /* Bank 1 - FLASH
  */
-#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -573,12 +573,12 @@
 #else /* CONFIG_BOOT_ROM */
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -586,12 +586,12 @@
 
 /* Bank 1 - Boot ROM
  */
-#define CFG_BR1_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -602,25 +602,25 @@
 
 /* Bank 2 - 60x bus SDRAM
  */
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	 CFG_OR2_8COL
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL
 
-#define CFG_PSDMR	 CFG_PSDMR_8COL
-#endif /* CFG_RAMBOOT */
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /* Bank 3 - Dual Ported SRAM
  */
-#define CFG_BR3_PRELIM	((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR3_PRELIM	(P2SZ_TO_AM(CFG_DPSRAM_SIZE)	|\
+#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_7_CLK			|\
@@ -628,12 +628,12 @@
 
 /* Bank 4 - DiskOnChip
  */
-#define CFG_BR4_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR4_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
+#define CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV2			|\
 			 ORxG_SCY_9_CLK			|\
@@ -641,35 +641,35 @@
 
 /* Bank 5 - FDC37C78 controller
  */
-#define CFG_BR5_PRELIM	((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 			 BRx_PS_8			  |\
 			 BRx_MS_GPCM_P			  |\
 			 BRx_V)
 
-#define CFG_OR5_PRELIM	(P2SZ_TO_AM(CFG_FDC37C78_SIZE)	  |\
+#define CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)	  |\
 			 ORxG_ACS_DIV2			  |\
 			 ORxG_SCY_10_CLK		  |\
 			 ORxU_EHTR_8IDLE)
 
 /* Bank 6 - Board control registers
  */
-#define CFG_BR6_PRELIM	((CFG_BCRS_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR6_PRELIM	((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR6_PRELIM	(P2SZ_TO_AM(CFG_BCRS_SIZE)	|\
+#define CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_SCY_7_CLK)
 
 /* Bank 7 - VME Extended Access Range
  */
-#define CFG_BR7_PRELIM	((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR7_PRELIM	((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_32			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR7_PRELIM	(P2SZ_TO_AM(CFG_VMEEAR_SIZE)	|\
+#define CONFIG_SYS_OR7_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_7_CLK			|\
@@ -677,12 +677,12 @@
 
 /* Bank 8 - VME Standard Access Range
  */
-#define CFG_BR8_PRELIM	((CFG_VMESAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR8_PRELIM	((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR8_PRELIM	(P2SZ_TO_AM(CFG_VMESAR_SIZE)	|\
+#define CONFIG_SYS_OR8_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_7_CLK			|\
@@ -690,12 +690,12 @@
 
 /* Bank 9 - VME Short I/O Access Range
  */
-#define CFG_BR9_PRELIM	((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR9_PRELIM	((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16			  |\
 			 BRx_MS_GPCM_P			  |\
 			 BRx_V)
 
-#define CFG_OR9_PRELIM	(P2SZ_TO_AM(CFG_VMESIOAR_SIZE)	  |\
+#define CONFIG_SYS_OR9_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)	  |\
 			 ORxG_CSNT			  |\
 			 ORxG_ACS_DIV1			  |\
 			 ORxG_SCY_7_CLK			  |\