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| author | Jon Loeliger <jdl@freescale.com> | 2008-01-03 09:46:55 -0600 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-01-03 09:46:55 -0600 |
| commit | 2c3536425d987bf079258973e2acebaaef3e16b6 (patch) | |
| tree | 659d06dd33eca4888e1f6d01d046507b76dc2d27 /include/configs/CPCI405AB.h | |
| parent | f743931f9b4d4e15c9bdfe726bef033ea1f1402c (diff) | |
| parent | ce37422d0002e10490e268392e0c4e3028e52cec (diff) | |
| download | u-boot-imx-2c3536425d987bf079258973e2acebaaef3e16b6.zip u-boot-imx-2c3536425d987bf079258973e2acebaaef3e16b6.tar.gz u-boot-imx-2c3536425d987bf079258973e2acebaaef3e16b6.tar.bz2 | |
Merge commit 'wd/master'
Diffstat (limited to 'include/configs/CPCI405AB.h')
| -rw-r--r-- | include/configs/CPCI405AB.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 4994319..1e9597d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -288,16 +288,6 @@ #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * |