summaryrefslogtreecommitdiff
path: root/include/configs/CPCI405.h
diff options
context:
space:
mode:
authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /include/configs/CPCI405.h
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
downloadu-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip
u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz
u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'include/configs/CPCI405.h')
-rw-r--r--include/configs/CPCI405.h184
1 files changed, 92 insertions, 92 deletions
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 2e948f5..3493d75 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -50,7 +50,7 @@
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
@@ -99,43 +99,43 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#undef CFG_HUSH_PARSER /* use "hush" command parser */
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
-#define CFG_BASE_BAUD 691200
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
+#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
+#define CONFIG_SYS_BASE_BAUD 691200
/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_LOOPW 1 /* enable loopw command */
@@ -160,16 +160,16 @@
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
-#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
-#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
+#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
+#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* IDE/ATA stuff
@@ -179,58 +179,58 @@
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
-#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-#define CFG_ATA_BASE_ADDR 0xF0100000
-#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFFD0000
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
+#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
-#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
-#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
-#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
+#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
+#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
+#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
#if 1 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
@@ -239,7 +239,7 @@
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CONFIG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
+ (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
#else /* Use EEPROM for environment variables */
@@ -253,17 +253,17 @@
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* Init Memory Controller:
@@ -279,54 +279,54 @@
*/
/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CFG_EBC_PB0AP 0x92015480
-#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP 0x92015480
+#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CFG_EBC_PB1AP 0x92015480
-#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP 0x92015480
+#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
-#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (CompactFlash IDE) initialization */
-#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 4 (NVRAM) initialization */
-#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
-#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
+#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 5 (Quart) initialization */
-#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
/*-----------------------------------------------------------------------
* FPGA stuff
*/
/* FPGA program pin configuration */
-#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
-#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
+#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
+#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
+#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
#if 1 /* test-only */
-#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
+#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
#else
-#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
#endif
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*