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authorWolfgang Denk <wd@denx.de>2010-08-11 09:38:31 +0200
committerWolfgang Denk <wd@denx.de>2010-09-19 19:29:46 +0200
commit36116650440406f99cc2c309f8f7c8388da46241 (patch)
treeb2b8cbc4eb56ab7cce709f851fcda8d2f5e801b2 /include/configs/CPC45.h
parentbf56080769f13025daaeb80d967eea19e7f78d60 (diff)
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Cleanup use of CONFIG_SYS_SRAM_BASE and CONFIG_SYS_SRAM_SIZE
Traditionally many boards used local definitions for SRAM base address and size (like SRAM_BASE, SRAM_LEN and/or SRAM_SIZE), while the (now) "official" names are CONFIG_SYS_SRAM_BASE and CONFIG_SYS_SRAM_SIZE. The corresponding code in arch/powerpc/lib/board.c was board specific, and has never actually been maintained well. Replace this by feature- specific code and adapt the boards that actually use this. NOTE: there is still a ton of boards using the old #defines, which therefor contain incorrect values in bi_sramstart and bi_sramsize. All respective board maintainers are requested to clean up their respective configurations. Thanks. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs/CPC45.h')
-rw-r--r--include/configs/CPC45.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index 91d262a..668cfa2 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -347,13 +347,12 @@
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define SRAM_BASE 0x80000000 /* SRAM base address */
-#define SRAM_END 0x801FFFFF
/*----------------------------------------------------------------------*/
/* CPC45 Memory Map */
/*----------------------------------------------------------------------*/
#define SRAM_BASE 0x80000000 /* SRAM base address */
+#define SRAM_END 0x801FFFFF
#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
#define BCSR_BASE 0x80600000 /* board control / status registers */
@@ -361,6 +360,8 @@
#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
+#define CONFIG_SYS_SRAM_BASE SRAM_BASE
+#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
/*---------------------------------------------------------------------*/
/* CPC45 Control/Status Registers */